1.1.6 · HinglishHow Computers Work

Combinational logic — half adder, full adder, multiplexer, decoder

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1.1.6 · Coding › How Computers Work


1. Core idea — WHY hume adders, muxes, decoders chahiye

WHY ye char?

  • Half/Full adder → taaki computer binary arithmetic kar sake (numbers add kare).
  • Multiplexer (MUX) → taaki hum bahut signals mein se ek select kar sake (data routing).
  • Decoder → taaki hum ek binary code se exactly ek output line activate kar sake (memory address karna, instructions choose karna).

2. Half Adder — do single bits add karna

Truth table se derive karo (first principles):

Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

WHY ye table? Bas binary mein count karo: , toh Sum, Carry.

HOW hum ek truth table ko gates mein convert karte hain? Wo rows dhundho jahan output hai.

  • Sum tab hai jab alag hon → ye exactly XOR hai:
  • Carry tab hai jab dono hon → ye AND hai:

3. Full Adder — do bits plus ek carry-in add karna

Truth table (3 inputs):

Sum
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Sum derive karo: Sum jab mein s ki count odd ho. Teen bits ki odd-parity exactly chained XOR hai:

Carry-out derive karo: jab kam se kam do inputs hon (majority). Table se:

WHY ye step? Wo rows list karo jahan : — har ek mein ek aisa pair hai jo dono hai, jo kisi ek AND term se capture hota hai.

Figure — Combinational logic — half adder, full adder, multiplexer, decoder

4. Multiplexer (MUX) — data selector

2-to-1 MUX derive karo (1 select line ):

  • Jab → output .
  • Jab → output .

Use use Boolean mein convert karo: har input ko select condition ke through "gate" karo.

WHY ye kaam karta hai: sirf tab pass karta hai jab ho (doosra term hota hai); sirf tab pass karta hai jab ho. Kabhi bhi sirf ek hi term active hoti hai.


5. Decoder — binary code → one-hot

2-to-4 decoder derive karo: har output tab hona chahiye jab inputs binary mein ke barabar hon. Ye minterm hai:

WHY: sirf tab true hai jab ho, matlab input . Har output inputs ke true/complement form ka ek AND hai.


6. The 80/20 — sach mein kya yaad rakhna hai


Flashcards

Combinational circuit ko kya define karta hai?
Output sirf current inputs par depend karta hai; koi memory/state/clock nahi.
Half adder Sum expression?
Half adder Carry expression?
Half-adder Sum XOR kyun hai OR kyun nahi?
OR galti se 1 output karta hai jab dono inputs 1 hon; XOR us case ko exclude karta hai (wo carry ban jata hai).
Full adder Sum expression?
(teen bits ki odd parity).
Full adder Carry-out expression?
(majority function).
Full adder banane ke liye kitne half adders + gates chahiye?
Do half adders + ek OR gate.
2-to-1 MUX output equation?
MUX ki select lines kya control karti hain?
Kaun sa data input single output tak route hoga (ye output value mein appear nahi hoti).
2-to-4 decoder input 10 ke liye kya output deta hai?
One-hot 0100 (sirf high).
Decoder line ka general output?
Inputs ka -wa minterm.
Decoder + OR gates koi bhi Boolean function kaise implement karte hain?
Function ki 1-rows ke corresponding minterm outputs ko OR kar do.

Recall Feynman: ek 12-saal ke bachche ko explain karo

Socho tum do LEGO-coin piles add kar rahe ho, lekin har jagah sirf EK coin aa sakta hai. Half adder: do coins saath rakkho; agar dono hain toh do ho jaenge, toh ek ko "carry" ke roop mein agle jagah de do — ye carry-keeping AND hai, aur "yahan bacha hua" XOR hai. Full adder: same hai, lekin ab ek dost pichli jagah se tumhe ek coin aur deta hai. Multiplexer: ek TV remote jo, channel number press karne par, sirf EK channel ko through aane deta hai. Decoder: tum ek number zor se bolte ho, aur exactly ek light bulb jis par wo number likha hai jal uthti hai.

Connections

Concept Map

output f of inputs only

built from

combine into

combine into

combine into

Sum = A XOR B

Carry = A AND B

add carry-in

Sum = A XOR B XOR Cin

Cout = majority

chained for

selects one signal

activates one line

Combinational logic

No memory / no clock

AND OR NOT XOR

Half adder

Multiplexer

Decoder

Sum bit

Carry bit

Full adder

Odd parity

Carry-out

Binary arithmetic

Data routing

Memory addressing