Radiation effects — TID, SEE, displacement damage

3.6.35 · Physics › Spacecraft Structures & Systems Engineering

Core Concept

Space radiation electronics ko teen alag physical mechanisms se damage karta hai: Total Ionizing Dose (TID), Single Event Effects (SEE), aur Displacement Damage (DD). Har mechanism semiconductor device physics ke alag-alag aspects ko attack karta hai, isliye alag-alag mitigation strategies chahiye hoti hain.

Total Ionizing Dose (TID)

Physical Mechanism — TID Electronics ko Kyun Damage Karta Hai

Step 1: Oxide mein Ionization Jab koi energetic particle (electron, proton, heavy ion) silicon dioxide insulating layers se guzarta hai:

$E_{\text{deposited}}=\int \frac{dE}{dx}ds$

jahaan $\frac{dE}{dx}$ linear energy transfer (LET) hai — energy lost per unit path length.

Yeh kyun matter karta hai: SiO₂ ka bandgap ~9 eV hai. 1 MeV proton ek 1 μm oxide layer mein ~10⁵ electron-hole pairs banata hai.

Step 2: Charge separation Electrons (mobile) nanoseconds mein electric fields se sweep ho jaate hain. Holes (SiO₂ mein kam mobile) dheere drift karte hain aur kaafi defect sites par trapped ho jaate hain:

$N_{\text{trapped}}=f\text{trap}\cdot \frac{\text{Dose}\cdot \rho \cdot t_{\text{ox}}}{E_{\text{pair}}}$

jahaan:

• $f_{\text{trap}}$ = trapping fraction (~0.01-0.3 SiO₂ ke liye)
• $\rho$ = material density
• $t_{\text{ox}}$ = oxide thickness
• $E_{\text{pair}}$ = electron-hole pair banane ki energy (~18 eV SiO₂ mein)

Yeh step kyun: Trapped positive charge ek electric field banata hai jo transistor threshold voltage ko shift kar deta hai.

Step 3: Threshold voltage shift MOSFET ke liye, trapped charge $Q_{\text{trap}}$ cause karta hai:

$\Delta V_{\text{th}}=-\frac{Q_{\text{trap}}}{C_{\text{ox}}}=-\frac{q\cdot N_{\text{trapped}}}{C_{\text{ox}}}$

jahaan $C_{\text{ox}}=\frac{{ϵ}_{\text{ox}}}{t_{\text{ox}}}$ oxide capacitance per unit area hai.

Physical insight: N-channel ke liye negative shift (device aasaan se turn on hota hai, leakage badhti hai). P-channel ke liye positive shift (turn on hone mein fail ho sakta hai).

$\text{TID}(t)={\int }_0^t{D}_{\text{rate}}(\vec{r}(t^{\prime }),\text{shielding})d{t}^{\prime }$

Typical rates:

• LEO (IS altitude): 1-10 rad/day, 2.5 mm Al ke peeche
• GEO: 10-100 rad/day (electrons dominant)
• Interplanetary: ~10 rad/day (solar/galactic cosmic rays)

Derivation note: Actual dose orbital inclination, solar cycle (trapped electron populations ko affect karta hai), aur shielding geometry par depend karti hai.

Step 1: Dose rate estimate karo AP-8/AE-8 trapped particle models use karke: $D_{\text{rate}}\approx 5\text{ rad(Si)/day}$

Step 2: Total dose calculate karo ${\text{TID}}_{5\text{yr}}=5\frac{\text{rad}}{\text{day}}\times 365\times 5=9125\text{ rad}$

Step 3: Device rating check karo Agar microcontroller 10 krad rated hai (typical commercial CMOS):

• Margin: 10,000 - 9,125 = 875 rad (~10% margin — inadequate!)
• Risk: Threshold shifts → increased leakage → thermal runaway

Yeh step kyun matter karta hai: Dose rate models mein uncertainties, manufacturing variations, aur dose rate effects ke liye 2-3× margin chahiye (low dose rates kuch oxides mein ZYADA damage kar sakte hain annealing competition ki wajah se).

Fix: Rad-hard CMOS (100 krad+) use karo ya aur shielding daalo (exponential diminishing returns — 10 mm Al sirf ~2× dose reduce karta hai).

Single Event Effects (SEE)

Physical Mechanism — Ionization Track se Bit Flip tak

Step 1: Charge deposition Ek heavy ion (jaise, galactic cosmic rays ka Fe⁵⁶) jiska LET = 40 MeV·cm²/mg hai, ek transistor se guzarta hai:

$Q_{\text{collected}}=\frac{\text{LET}\cdot \rho \cdot L}{E_{\text{pair}}}$

jahaan $L$ sensitive depth hai (~1-10 μm).

Example: Silicon mein ($\rho =2.33$ g/cm³, $E_{\text{pair}}=3.6$ eV): $Q_{\text{collected}}=\frac{40\times 10^6\text{ eV}\cdot 2.33{\text{ g/cm}}^3\cdot 5\times 10^{-4}\text{ cm}}{3.6\text{ eV}}\times 1.6\times 10^{-19}\text{ C}\approx 2\text{ pC}$

Step 2: Charge collection Charge drift (depletion region mein, fast ~ps) aur diffusion (neutral regions mein, slower ~ns) se collect hoti hai:

$I(t)=I_{\text{drift}}(t)+I_{\text{diff}}(t)$

Modern nanoscale devices mein peak current milliamps tak pahunch sakta hai.

Step 3: Circuit response Agar collected charge critical charge $Q_{\text{crit}}$ se zyada ho:

$Q_{\text{crit}}=C_{\text{node}}\cdot V_{\text{crit}}$

jahaan $C_{\text{node}}$ node capacitance hai aur $V_{\text{crit}}$ woh voltage swing hai jo state flip karne ke liye chahiye.

Chhota kyun zyada vulnerable hai: Modern 7 nm nodes mein $C_{\text{node}}\sim 0.1$ fF hai, isliye $Q_{\text{crit}}\sim 0.1$ fC — 1990s technology se 100× zyada sensitive.

$R_{\text{SE}}=\int \sigma (\text{LET})\cdot \Phi (\text{LET})d(\text{LET})$

jahaan:

• $\sigma (\text{LET})$ = diye gaye LET par SE ke liye cross-section (effective area), cm²/bit mein
• $\Phi (\text{LET})$ = particle flux vs. LET, particles/(cm²·sr·s·MeV·mg⁻¹·cm²) mein

Cross-section ke liye Weibull fit: $\sigma (\text{LET})={\sigma }_{\text{sat}}\left(1-e^{-{\left(\frac{\text{LET}-{\text{LET}}_{\text{th}}}{\lambda }\right)}^s}\right)$

• ${\text{LET}}_{\text{th}}$ = threshold LET jiske neeche koi upset nahi hota
• ${\sigma }_{\text{sat}}$ = saturation cross-section (geometric device area)
• $\lambda ,s$ = fitting parameters

Step 1: GEO heavy ion flux lo Solar minimum ke liye CREME96 model use karke: ${\Phi }_{\text{total}}\approx 10{\text{ ions/(cm}}^2\text{⋅day)}\text{ for LET}>5{\text{ MeV⋅cm}}^2\text{/mg}$

Step 2: Upset rate per bit calculate karo $R_{\text{bit}}={\sigma }_{\text{sat}}\cdot {\Phi }_{\text{total}}=10^{-7}{\text{ cm}}^2\times 10\frac{\text{ions}}{{\text{cm}}^2\text{⋅day}}=10^{-6}\text{ upsets/(bit⋅day)}$

Step 3: Total device upset rate $R_{\text{device}}=R_{\text{bit}}\times N_{\text{bits}}=10^{-6}\times 10^9=10^3\text{ upsets/day}$

Yeh kyun matter karta hai: ~1 upset per minute — error correction ke bina unusable!

Mitigation: EDAC (Error Detection And Correction) — jaise Hamming codes ~12% overhead add karte hain lekin saare single-bit errors correct karte hain, double-bit errors detect karte hain.

Single Event Latchup (SEL) — The Destructive Mode

Mechanism: Ionization track CMOS mein parasitic PNPN thyristor structure trigger karta hai:

1. Heavy ion electron-hole pairs banata hai
2. Electrons/holes nearby wells mein drift karte hain
3. Parasitic NPN aur PNP bipolar transistors activate hote hain
4. Positive feedback: $I_{\text{latch}}=\frac{V_{\text{dd}}}{R_{\text{on}}}$ → 1 A se zyada ho sakta hai → device destruction

Current latchup physics: ${\alpha }_{\text{PNP}}\cdot {\alpha }_{\text{NPN}}>1$

jahaan $\alpha$ parasitic bipolars ke current gains hain.

Modern CMOS kyun safer hai: Triple-well processes n-wells ko p-substrate se isolate karte hain, ek parasitic path tod ke.

Displacement Damage

Physical Mechanism — Non-Ionizing Energy Loss (NIEL)

Step 1: Nuclear collision Kinetic energy $E_p$ wala incoming proton silicon nucleus se scatter karta hai:

$E_{\text{recoil}}=\frac{4M_p{M}_{\text{Si}}}{(M_p+M_{\text{Si}}{)}^2}{E}_p{\sin }^2(\theta /2)$

Maximum recoil energy: head-on collision ke liye $E_{\text{max}}\approx 0.13\cdot E_p$.

Displacement ka threshold: Si ke liye $E_d\approx 25$ eV — ionization threshold se kaafi kam.

Step 2: Cascade Agar $E_{\text{recoil}}>E_d$, toh recoiling Si atom (PKA = Primary Knock-on Atom) ek displacement cascade banata hai:

$N_{\text{displaced}}\approx \frac{E_{\text{recoil}}}{2E_d}$

10 MeV proton ek hi collision mein ~30,000 atoms displace kar sakta hai!

Step 3: Defect formation Zyaatar displaced atoms jaldi recombine ho jaate hain. Stable defects initial displacements ke ~0.1-1% par bante hain:

• Vacancy (V): missing Si atom
• Interstitial (I): lattice sites ke beech extra Si atom
• Complexes: V-O (vacancy-oxygen), V-V, etc.

Yeh Shockley-Read-Hall recombination centers ki tarah kaam karte hain.

$\frac{1}{\tau (\Phi )}=\frac{1}{{\tau }_0}+K_{\tau }\cdot {\Phi }_{\text{eq}}$

jahaan:

• ${\tau }_0$ = initial lifetime
• $K_{\tau }$ = damage coefficient (material/device dependent)
• ${\Phi }_{\text{eq}}$ 1 MeV neutron equivalent fluence (saare particles 1 MeV neutron NIEL se normalize kiye gaye)

Equivalent fluence: ${\Phi }_{\text{eq}}=\int \frac{\text{NIEL}(E)}{{\text{NIEL}}_{\text{1 MeV n}}}\cdot \Phi (E)dE$

Step 1: Equivalent fluence calculate karo GEO proton spectrum (trapped belts) ~$10^{11}$ protons/(cm²·year) equivalent deta hai.

${\Phi }_{\text{eq, 10yr}}=10^{12}{\text{ MeV-n-eq/cm}}^2$

Step 2: Damage equation apply karo GaAs solar cells ke liye: $\frac{P(\Phi )}{P_0}=1-C{\log }_{10}\left(1+\frac{{\Phi }_{\text{eq}}}{{\Phi }_x}\right)$

Typical: $C=0.03$, ${\Phi }_x=3\times 10^{10}$ cm⁻².

$\frac{P(10^{12})}{P_0}=1-0.03{\log }_{10}\left(1+\frac{10^{12}}{3\times 10^{10}}\right)=1-0.03\times 1.52=0.954$

Result: Sirf displacement damage se 4.6% power loss.

Yeh step kyun: Arrays ko 1/(1-degradation) = 1.048× ya ~5% oversize karna padega taaki end-of-life power maintain ho sake.

Step 3: TID effects bhi add karo Coverglass darkening (glass mein TID) aur ~2-3% loss add karta hai → total 7-8% degradation → arrays ko beginning-of-life requirement ka 1.08× size karo.

Comparison Table — Jaano Kis Threat se Lad Rahe Ho

Steel-man: Low-energy particles ke liye (< 10 MeV), haan. Galactic cosmic ray heavy ions (GeV energies) ke liye, shielding almost useless hai — 1 meter aluminum bhi sirf ~2× flux reduce karta hai.

Aur bura: Shielding nuclear fragmentation se secondary particles banata hai. Aluminum se takrata high-energy proton neutrons, pions, light ions produce karta hai — kabhi-kabhi shield ke peeche dose badh jaati hai!

The nuance:

• TID: Shielding thickness optimize karo (typical 2-5 mm Al)
• Heavy ions se SEE: Shielding ineffective → EDAC, redundancy, rad-hard design use karo
• Protons se SEE: Moderate shielding help karta hai (protons ions se kam penetrating hain)

Sahi approach: Dose-depth curves — apni specific orbit aur particle environment ke liye dose vs. shielding thickness calculate karo. Ek optimal thickness hoti hai jiske baad sirf mass add ho raha hota hai.

Failure mode: Ground testing use karta hai:

• High dose rates (1-100 rad/s) — actual space mein 10⁻⁵ rad/s hota hai
• Room temperature — orbit mein -40°C se +80°C ho sakta hai
• Specific test particles — actual orbit mein mixed spectrum hota hai

Low dose rate enhancement (LDRE): Kuch oxides ZYADA damage dikhate hain low dose rates par kyunki slow hole trapping annealing se compete karta hai. Ek part jo high rate par 100 krad pass karta hai woh orbit par 50 krad mein fail ho sakta hai!

Temperature effects: High temps par annealing speed up hoti hai (TID mein help karta hai), lekin kuch defects zyada stable hote hain (DD worsens karta hai).

Fix:

1. Mission-relevant dose rates aur temps par testing request karo
2. Uncertainty factors apply karo (critical parts ke liye 2×)
3. Proven flight performance wale heritage parts use karo

Mitigation Strategy Matrix

TID mitigation:

• Rad-hard-by-design (RHBD) processes (SOI, enclosed-gate transistors)
• Shielding optimization
• Device selection (mission dose + margin tak test karo)
• Voltage derating (lower E-fields trapping kam karte hain)

SEE mitigation:

• SEU: EDAC, TMR (Triple Modular Redundancy), scrubbing
• SEL: Current limiting, watchdog timers, latchup-immune processes
• SEB/SEGR: Voltage derating, device selection (wide-bandgap materials)

DD mitigation:

• Solar arrays oversize karo
• High initial lifetime wale devices select karo
• DD ke liye kam sensitive materials use karo (solar cells ke liye InGaP, Si se better hai)
• Effective shielding nahi hoti — degradation ke around design karo

TID jaisa hai ki tumhare phone ke circuits ki deewarein saalon mein dheere-dheere maili hoti jaayein. Gandagi jamti rehti hai (trapped electric charges), aur aakhirkar buttons sahi se kaam nahi karte (transistors ka on/off hona badal jaata hai).

SEE jaisa hai ki ek lightning bolt tumhare phone ki memory mein girti hai. Achanak ek 0, 1 ban jaata hai, aur tumhara saved game corrupt ho jaata hai. Ya phir aur bura — ek short circuit banta hai jo chip ko turant fry kar deta hai!

Displacement damage jaisa hai ki koi tumhara phone itni zor se hilaaye ki solar panel mein atoms apni jagah se knock ho jaayein. Panel kaam toh karta hai lekin kam electricity banata hai kyunki uski structure mein tiny holes aa gayi hain.

Engineers isse is tarah handle karte hain:

• Zyada mazboot "space-grade" electronics use karke (jaise rugged phone case, lekin circuits ke liye)
• Har cheez ki backup copies rakhke (agar ek memory bit flip ho, do aur copies vote karke use theek kar deti hain)
• Solar panels zaroorat se bade banaake taaki jab woh kamzor ho jaayein, tab bhi kaafi power ho

Isliye space ka saamaan itna mehenga hota hai — har cheez ko saalon tak is invisible bullet storm mein survive karna padta hai!

Visual: TID hai rust, SEE hai lightning, DD hai termites

Connections

• Spacecraft Orbits — orbit radiation environment determine karta hai (LEO vs GEO vs interplanetary)
• Van Allen Belts — trapped proton/electron belts Earth orbit ke liye primary TID/DD source hain
• Solar Activity Cycles — solar max/min trapped electron populations ko affect karta hai (10× factor)
• Semiconductor Physics — band structure, oxides mein E-field, minority carrier lifetime teeno mechanisms ko underpin karte hain
• Error Correcting Codes — SEU mitigation ke liye Hamming, Reed-Solomon
• Photovoltaic Systems — DD se solar cell degradation
• Power Budget — solar array degradation 5-10% account mein leni chahiye
• Reliability Engineering — FIT rates, bathtub curve radiation-induced infant mortality se affect hote hain

#flashcards/physics

Spacecraft electronics mein teen primary radiation damage mechanisms kaunse hain? :: Total Ionizing Dose (TID), Single Event Effects (SEE), aur Displacement Damage (DD).

Teen SEU mitigation techniques batao :: Error Detection And Correction (EDAC), Triple Modular Redundancy (TMR), aur periodic memory scrubbing.

Concept Map