6.5.17 · D3 · HinglishAdvanced & Emerging Architectures

Worked examplesWafer-scale engines (Cerebras-style)

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6.5.17 · D3 · Hardware › Advanced & Emerging Architectures › Wafer-scale engines (Cerebras-style)

Yeh page Wafer-scale engines (Cerebras-style) ki "numbers daalo aur crank ghuma do" companion hai. Koi bhi number chhune se pehle, hum har tarah ke questions lay out karte hain jo yeh topic pooch sakta hai, taaki jab exam mein koi mile toh tumhe already pata ho ki woh kis cell mein baithta hai — aur koi scenario surprise na kare.

Yahan istemaal kiye gaye har symbol ko pehle parent note mein define kiya gaya tha. Hum har ek ko wahin re-state karte hain jab woh appear karta hai, toh tumhe kabhi scroll back nahi karna padega.


Symbols, use se pehle define kiye gaye

Kyunki neeche ka scenario matrix pehle se formulas naam leta hai, hum har symbol ko pehle pin karte hain, taaki koi bhi letter apne plain-words meaning se pehle na aaye.


Scenario matrix

Poore topic ko ek grid ki tarah socho. Har row ek quantity hai jo compute karne ke liye poochi ja sakti hai; har column ek regime hai (tiny/normal/extreme, ya ek degenerate edge). Hume neeche har filled cell cover karni hai. Table mein saare symbols abhi seedha upar define kiye gaye hain.

Cell Quantity Regime being tested Worked in
A Monolithic yield Small die (near 1) Ex. 1
B Monolithic yield Whole-wafer die (near 0, the "killer") Ex. 1
C Yield limit Degenerate: aur Ex. 2
D Over-provisioning Normal fail fraction Ex. 3
E Over-provisioning Edge: aur Ex. 3
F Aggregate bandwidth Order-of-magnitude compare vs GPU Ex. 4
G Mesh hop latency Neighbour (best) vs corner-to-corner (worst) Ex. 5
H Aggregate SRAM capacity "Kya model fit hoga?" word problem Ex. 6
I Sparsity speedup Skip kiye gaye zeros ka fraction Ex. 7
J Combined exam twist Yield aur capacity aur bandwidth saath mein Ex. 8

Kisi bhi arithmetic se pehle, yahan poora matrix pictures mein drawn hai. Neeche har panel ek formula ki shape hai — pehle inhe dekho, phir numbers woh curves par sirf points honge jo tum pehle se dekh chuke ho.

Figure — Wafer-scale engines (Cerebras-style)

Alt text: chaar chhhote pastel panels. Top-left — yield curve die area badhne ke saath 1 se 0 ki taraf girti hui, jisme small-die point (green, high) aur whole-wafer point (coral, floor-crushed) marked hain. Top-right — provisioning factor dheere badhta hua phir infinity ki taraf shoot karta hua jaise . Bottom-left — aggregate bandwidth ek single short GPU bar ke upar towering 850k parallel links ka tall stack. Bottom-right — ek mesh grid jisme ek short green best-case hop aur ek long coral worst-case corner-to-corner path hai.


Example 1 — Cells A & B: yield killer, small die vs whole wafer

Neeche wali figure answer ki shape hai: yield curve aur jahan hamare do dies us par land karte hain.

Figure — Wafer-scale engines (Cerebras-style)

Alt text: yield curve die area ke against plot ki gayi. Ek green dot small 800 mm² die ko curve par neeche mark karta hai; ek coral dot 46,000 mm² wafer ko zero axis par crush hue mark karta hai, jisme ek dashed guide dikhata hai ki curve kitni tezi se collapse hoti hai.

Step 1 — Har ke liye mean defect count compute karo. Yeh step kyun? Symbols box se yaad karo ki ek die mein expected average number of killing defects hai, aur yeh ke barabar hai. Exponential tabhi samajh aata hai jab hum yeh average jaante hain; yahi woh single knob hai jis par sab kuch depend karta hai.

Step 2 — Poisson zero-defect probability apply karo. Yeh step kyun? Ek die tabhi good hai jab usme zero killing defects aayein, aur mean ke saath zero events ki Poisson probability hai (parent note ki derivation se).

Step 3 — Matrix cells ke against interpret karo. Yeh step kyun? Akele numbers nahi sikhate; regime sikhata hai. Cell A (small die) pehle se hi terrible hai; cell B (whole wafer) astronomically, unimaginably zero hai — yeh figure mein floor par pinned coral dot hai.

Recall

physically kya matlab hai? Universe mein atoms se zyada wafers banane padenge ek perfect aane se pehle ::: yahi exactly woh reason hai kyun ek defect-free monolithic wafer impossible hai, jo redundancy trick ko force karta hai.

Verify: Units check — hai dimensionless, ek exponent ke liye sahi. Sanity: bada chhota , aur dono aur ke beech hain. ✓

Poori derivation lineage ke liye Yield & Defect Density Models dekho.


Example 2 — Cell C: yield ki do degenerate limits

Example 1 figure mein yield curve ko phir dekho: dono degenerate corners curve ko uske left edge par wapas le jaate hain, jahan ya vanish hota hai aur height par wapas aati hai.

Step 1 — Limit ko exponent mein substitute karo. Yeh step kyun? Degenerate inputs test karte hain ki formula sane rehta hai ya nahi. Dono cases mein exponent .

Step 2 — Matlab padho. Yeh step kyun? Exactly ki yield matlab "hamesha kaam karta hai." Ek flawless process (koi defects nahi) ya ek infinitesimal die (hit karne ke liye kuch nahi) dono success guarantee karte hain — formula sahi tarah certainty return karta hai.

Verify: continuous hai aur ; dono limits agree karte hain. ✓


Example 3 — Cells D & E: cores ko over-provision karna, normal aur edge

Figure provisioning factor dikhata hai: ke paas gentle, phir par ek wall. Hamare teen cases is curve par teen dots hain.

Figure — Wafer-scale engines (Cerebras-style)

Alt text: over-provision factor ka curve fail fraction ke against. Left par flat aur 1 ke paas; par ek green dot 1.1 se thoda upar; par ek lavender dot exactly 1 par; aur par ek coral arrow jahan curve infinity ki taraf shoot karta hai.

Step 1 — ko over-provision formula mein daalo. Yeh step kyun? Factor "insurance premium" hai — kitne spare cores banane hain taaki ke marne ke baad enough survive karein. Figure par yeh green dot hai, 1 se barely upar.

Toh ~944k cores banao 850k survivors guarantee karne ke liye — lagbhag 11% extra.

Step 2 — Edge lo. Yeh step kyun? Zero failures ko koi spare demand nahi karni chahiye — lavender dot exactly height 1 par baitha hai.

Step 3 — Edge lo. Yeh step kyun? Agar almost har core fail ho, toh almost infinite chahiye. Denominator , toh — figure mein coral wall, formula chilla raha hai "yeh process unusable hai."

Verify: monotonic — jaise badhta hai , badhta hai . Check (a): ? Yeh inequality satisfy karne ke liye round up hota hai; exact use karne par exactly milta hai. ✓


Example 4 — Cell F: aggregate bandwidth vs ek GPU

Figure scale ko visceral banata hai: parallel links ka ek towering stack ek single short GPU bar ke saath.

Figure — Wafer-scale engines (Cerebras-style)

Alt text: log scale par bar chart jo WSE aggregate bandwidth (850,000 GB/s, tall lavender bar) ko ek single GPU link (900 GB/s, short coral bar) se compare karta hai, jisme ~944× ratio ek arrow se annotated hai.

Step 1 — Links ko sum karo (woh parallel chhalte hain). Yeh step kyun? Mesh mein har link simultaneously data carry karta hai, toh total = simple sum. Yahi additivity hai jis wajah se wafer-scale bandwidth huge hai — Network-on-Chip (NoC) & Mesh Topologies.

Step 2 — GPU number se divide karo. Yeh step kyun? Ek absolute number kuch matlab nahi rakhta; ratio woh headline hai "kyun yeh jeetta hai."

Toh ~944×, yaani roughly parent note mein quoted "1000×."

Verify: unit check — GB/s sum karne se GB/s milta hai; ratio dimensionless hai. (decimal SI mein use karke). ✓ Dennard Scaling & the Memory Wall problem se relate karta hai jise yeh solve karta hai.


Example 5 — Cell G: mesh hop latency, best vs worst case (geometric)

Figure — Wafer-scale engines (Cerebras-style)

Alt text: lavender core squares ki ek mesh grid. Ek short green arrow best case mark karta hai — neighbours ke beech ek single hop (1 ns). Ek long coral staircase path worst case ko corner se corner tak rows phir columns ke saath trace karta hai (~2000 hops, ~2 µs). Start core aur far corner butter yellow mein highlighted hain.

Step 1 — Clock speed ko per-hop time mein convert karo. Yeh step kyun? Latency seconds mein hoti hai, hertz mein nahi. GHz par ek cycle frequency ka reciprocal hai.

Step 2 — Best case: ek hop. Yeh step kyun? Neighbours adjacent hain (figure mein green arrow) — ek single link. Yeh local, streaming traffic ke liye common case hai.

Step 3 — Worst case: grid ke across Manhattan distance. Yeh step kyun? 2-D mesh par tum sirf rows aur columns ke saath move kar sakte ho, toh grid ka corner-to-corner (figure mein coral staircase) ke liye hops hai — straight-line diagonal nahi.

Step 4 — Compare karo. Worst on-wafer latency bhi (~2 µs) best inter-server network hop ke barabar hai — aur locality nearly sab real traffic ko 1 ns par rakhti hai.

Verify: ✓; s s ✓. ke liye Manhattan distance , estimate ke liye 2000 par round kiya. Nearest-neighbour dataflow kyun efficient hai yeh jaanne ke liye Systolic Arrays & TPUs dekho.


Example 6 — Cell H: aggregate SRAM capacity (word problem)

Step 1 — Per-core SRAM sum karo. Yeh step kyun? Parent note ka key correction: capacity cores par sum hai, kabhi per-core nahi. Har core tiny hai; mesh vast hai.

Step 2 — GB mein convert karo. Yeh step kyun? Model ki requirement GB mein hai, toh units match karni hogi. Is page ke top par pinned decimal convention use karke, .

Step 3 — Model se compare karo. Yeh step kyun? Fit matlab capacity requirement.

Toh (a) ka answer hai GB aur (b) haan, model poori tarah on-wafer fit hota hai 10.8 GB headroom ke saath — koi external DRAM nahi chahiye.

Verify: kB GB ✓; GB headroom ✓.


Example 7 — Cell I: sparsity speedup

Step 1 — Work remaining = nonzero fraction. Yeh step kyun? Yaad karo fraction of activations that are zero hai. Sirf nonzero activations ek multiply trigger karte hain, toh useful work ke saath scale karta hai — Sparsity in Neural Networks.

Step 2 — Speedup = work done ka inverse. Yeh step kyun? Agar tum same rate par sirf ek quarter operations karo, toh tumhe quarter time mein kaam ho jaata hai.

Step 3 — Edge check . Yeh step kyun? All-zero → infinite speedup (karne ko kuch nahi), sensible limit; (dense) → speedup (koi benefit nahi), yahi wajah hai kyun dense GPUs yahan "kuch gain nahi karte."

Verify: ✓; limits , dono monotonic. ✓


Example 8 — Cell J: combined exam twist

Step 1 — Surviving cores. Yeh step kyun? Har cheez jo baad mein aati hai (memory, bandwidth) depend karti hai ki defects ke baad kitne cores alive hain. Yahan woh fraction hai jo fail hoti hai, toh survive karta hai.

Step 2 — Surviving SRAM. Yeh step kyun? Capacity sirf good cores par sum hoti hai — dead cores kuch contribute nahi karte. Decimal prefixes page ke top par pinned hain.

Step 3 — Survivors ki aggregate bandwidth. Yeh step kyun? Same additive-link logic jaisa Example 4 mein, lekin sirf live cores count hote hain.

Step 4 — Verdict. Teeno constraints pass hoti hain; tightest margin memory hai ( vs GB, sirf GB spare). Yeh kyun note karein? Exam mein, "kaun sa margin sabse patla hai" woh follow-up question hai — yahan memory binding constraint hai.

Verify: ✓; kB GB ✓; ✓; GB/s TB/s ✓.


Recall Matrix ka one-line recap

Yield exponentially area ke saath collapse hoti hai (Ex. 1–2), toh tum cores ko se over-provision karte ho (Ex. 3), phir survivors additive bandwidth deliver karte hain (Ex. 4, 8), 1-ns local / µs-worst latency (Ex. 5), summed SRAM capacity (Ex. 6, 8), aur sparsity throughput multiply karta hai (Ex. 7).

Related tooling context: Chiplets & 2.5D/3D Integration · Liquid Cooling & Power Delivery Networks · Hinglish version: 6.5.17 Wafer-scale engines (Cerebras-style) (Hinglish).