Wafer-scale engines (Cerebras-style): Question bank

6.5.17 · D5 · Hardware › Advanced & Emerging Architectures › Wafer-scale engines (Cerebras-style)

Shuru karne se pehle, symbols ka ek reminder taaki kuch bhi unearned na lage:

$D$ = defect density (defects per mm² randomly wafer pe bikhra hua).
$A$ = die area (mm² ek chip ka).
$Y = e^{- D A}$ = probability ki ek die mein zero killing defects hain.
$M$ = physically banaye gaye cores, $N$ = cores jo tumhe actually chahiye, $f$ = fraction jo mar sakta hai.
$B_{cor e}$ = bandwidth of one core = kitne bytes per second ek core apne neighbors ko push kar sakta hai (units: GB/s, yaani gigabytes per second).
$B_{t o t a l}$ = total bandwidth poore fabric ka = sabhi cores ki outgoing bandwidth ka sum ek saath (units: TB/s ya PB/s).

Traps mein do jargon words aate hain — yeh raha inka appearance usse pehle ke tum inse milo:

Aur yield idea aur rerouting trick bhi pictures ke roop mein hain, taaki neeche ke traps kisi cheez ka reference karein jo tumne pehle dekha ho:

True ya false — justify karo

Neeche har claim ya toh subtly true hai ya subtly false. Kabhi sirf ek word mein jawab mat do.

Ek wafer-scale engine poore wafer ko ek single connected die ki tarah use karta hai.

True — scribe lines (tiles ke beech blank streets) jo normally reticle fields ko alag karti hain, extra metal se bridge ki jaati hain taaki poora wafer ek mesh ban jaaye, yahi is design ki defining trick hai.

Ek WSE mein model hold karne ke liye external DRAM hota hai.

False — saara model state distributed on-chip SRAM mein rehta hai; koi external DRAM nahi hota, yahi cheez slow off-chip memory boundary ko remove karti hai.

Poisson yield model

Y = e^{- D A}

predict karta hai ki full-wafer monolithic die essentially kabhi kaam nahi karta.

True — jaise

A

poore wafer tak badhta hai,

D A ≫ 1

e^{- D A} \to 0

, matlab defect-free full wafer astronomically unlikely hai.

Kyunki

Y = e^{- D A} \to 0

, wafer-scale chips physically impossible hain.

False — formula sirf defect-free wafers ko kill karta hai; WSEs kabhi perfection demand nahi karte, woh redundancy aur reroutable mesh links use karte hain taaki kuch dead cores matter na karein.

On-wafer bandwidth cores ke across additive hai kyunki mesh links parallel mein chalte hain.

True — har core apne neighbor links simultaneously drive karta hai (har ek

B_{cor e}

bytes/s contribute karta hai), so

B_{t o t a l} = M \cdot B_{cor e}

;

M = 850, 000

cores ke saath

B_{cor e} = 1

GB/s pe yeh

850

TB/s hai.

Nearest-neighbor latency aur worst-case corner-to-corner latency ek mesh mein lagbhag same hote hain.

False — ek neighbor hop ~1 ns hai (1 GHz pe ek clock tick, kyunki

1/1 0^{9} s = 1

ns), lekin ~

1000 \times 1000

cores ka mesh (yahi tarika hai ~850,000 cores ko square grid mein arrange karne ka) corner-to-corner ~2000 hops hai, so ~2 µs; yeh design bet lagata hai ki traffic local hoga taaki zyada hops saste wale hon.

Zero-se-multiply skip karna (sparsity harvesting) time aur energy dono bachata hai.

True — ek zero activation koi kaam trigger nahi karta, so us multiply ke cycles aur switching energy dono avoid ho jaate hain.

WSE essentially sirf ek bahut bada GPU hai.

False — ek GPU shared-memory SIMT hai jo external HBM DRAM se backed hai; ek WSE ek distributed-memory mesh hai tiny cores ka sirf local SRAM ke saath, so iska memory model, programming model, aur bottlenecks sab alag hain (dekho Systolic Arrays & TPUs).

Cores ko

\frac{1}{1 - f}

factor se over-provision karna guarantee karta hai ki enough survive karein.

True —

M (1 - f) \geq N

se, dono sides ko positive number

(1 - f)

se divide karne par

M \geq \frac{N}{1 - f}

milta hai, so itna banana matlab expected good count abhi bhi target

N

meet karta hai.

Power wafer ke edges se, in-plane deliver ki jaati hai.

False — current vertically back se deliver kiya jaata hai (wafer ke perpendicular) taaki itni wide die pe lambi resistive drops na hon.

Error dhundho

Har statement mein ek flaw hai. Use ek sentence mein naam do.

"Model ek single core ke SRAM mein fit hona chahiye, so WSEs sirf tiny models run kar sakte hain."

Model sabhi cores mein sharded hota hai; capacity cores ke upar sum hai (tens of GB), per-core nahi, to mesh partial results ko stitch karta hai.

"Kyunki bade dies mein zyada transistors hote hain, wafer-scale ki sirf problem total wattage hai."

Asli dushman in-plane power delivery aur thermal expansion cracking solder hai, raw watts nahi — isliye vertical power aur liquid cooling exist karte hain (dekho Liquid Cooling & Power Delivery Networks).

"Yield engineering manufacturing process ko defect-free bana ke ki jaati hai."

Tum wafer ko defect-free nahi bana sakte; yield spare cores aur reroutable links se engineer ki jaati hai, metric ko 'enough good cores' pe redefine karte hue (dekho Yield & Defect Density Models).

Y = e^{- D A}

mein, area double karne se yield half ho jaati hai."

Yeh half nahi hoti —

A

double karna yield ko square karta hai, kyunki

e^{- D (2 A)} = (e^{- D A})^{2}

, so yield linearly se kahin zyada tezi se collapse hoti hai.

"Ek high-locality all-to-all workload mesh NoC ke liye ideal fit hai."

All-to-all traffic mesh ke liye poor locality hai — jab har core ko har doosre se baat karni ho tab iska nearest-neighbor advantage khatam ho jaata hai, so yeh tab hai jab WSE galat choice hai.

"Kyunki cores identical hain, ek broken core poore wafer ko scrap karne par majboor karta hai."

Reroutable mesh simply dead cores ke around route kar deta hai, so kuch failures built-in redundancy dwara absorb ho jaati hain wafer ko scrap karne ki bajaye.

"On-chip SRAM DRAM se slower hai, so data on-wafer rakhna speed pe ek compromise hai."

Bilkul ulta — har core apne apne SRAM tak ~1 cycle mein pahunchta hai aur aggregate bandwidth petabytes/second range mein hai, off-chip DRAM se kahin zyada (dekho Dennard Scaling & the Memory Wall).

Why questions

Sirf fact nahi, mechanism answer karo.

Yield formula mein koi aur function ki jagah

e^{- D A}

kyun aata hai?

Defects independently aur randomly girte hain, to ek fixed area mein unka count Poisson distribution follow karta hai; exactly zero defects ki probability,

P (0) = e^{- D A}

, wahi hai jo ek exponential naturally deta hai.

Scribe lines ko extra metal se bridge kyun karte hain instead of wafer ko ek die ki tarah shuru se design karne ke?

Stamping machine sirf ek reticle field (ek tile) ek time pe print kar sakti hai, so wafer janam leta hai alag tiles ke roop mein; baad mein blank scribe streets ke across wiring add karna un tiles ko bina lithography step change kiye ek connected mesh mein stitch karta hai (dekho Chiplets & 2.5D/3D Integration).

Unstructured sparsity WSE pe real speedup kyun hai lekin GPU ke liye mushkil hai?

Ek WSE core tab kaam karta hai jab koi nonzero activation aata hai, so scattered zeros naturally skip ho jaate hain; ek GPU ko apni lanes busy rakhne ke liye dense, structured math chahiye, to random zeros abhi bhi cycles kharchte hain (dekho Sparsity in Neural Networks).

Neural-net training ke liye raw FLOPs se zyada communication on-wafer kyun matter karta hai?

Training apna zyada tar time activations aur gradients shuffle karne mein spend karti hai, aur woh traffic chip boundaries cross karne par bottleneck ban jaata hai — use silicon pe rakhna slow, hot, energy-hungry hops ko remove karta hai.

Ek single mesh hop ki cost sirf ~1 ns kyun hoti hai?

Do cores physical neighbors hain jo micrometers apart baithe hain, to signal thodi si distance travel karta hai aur ek clock cycle mein latch ho jaata hai; 1 GHz clock pe ek cycle

1/1 0^{9}

s = 1 ns hai, to hop distance se nahi, clock se limited hai.

Cross-wafer in-plane power drops kyun prohibitive hain, jo vertical delivery ko force karte hain?

~215 mm wafer ke across stretched thin metal layer ki real resistance

R

hoti hai, aur usme tens of thousands of amps push karna

I^{2} R

heat se power waste karta hai aur edge se door voltage sag karta hai; current ko seedha back face se upar se khaana har core ka path short aur nearly equal banata hai, us drop ko khatam karte hue.

Cores ko over-provision kyun karte hain instead of jo survive kare usse accept karne ke?

Kyunki defect locations random hain, tum

N

good cores guarantee nahi kar sakte bina margin ke;

M \geq \frac{N}{1 - f}

build karna ensure karta hai ki expected survivors abhi bhi requirement meet karein (dekho Yield & Defect Density Models).

Nearest-neighbor mesh, all-to-all crossbar ki jagah, on-chip network kyun sahi choice hai?

Ek all-to-all fabric ko aisi wiring chahiye jo cores ki sankhya se kahin zyada tezi se badhti hai; ek 2-D mesh wiring ko local aur cheap rakhta hai, aur neural traffic mostly local hoti bhi hai (dekho Network-on-Chip (NoC) & Mesh Topologies).

Edge cases

Woh scenarios jinse reader ko surprise nahi hona chahiye.

Kya hota hai yield ka jab die area

A \to 0

D A \to 0

Y = e^{- D A} \to 1

— tiny dies almost hamesha kaam karti hain, yahi exactly woh reason hai ki industry historically wafers ko small chips mein kaatti thi.

Kya hota hai agar defect density

D = 0

ho?

Tab

Y = e^{0} = 1

kisi bhi area ke liye, so ek perfect wafer ko koi redundancy nahi chahiye — lekin real

D > 0

hamesha hota hai, so yeh sirf ek theoretical limit hai.

Kya hoga agar fail hone wala required core fraction

f \to 1

ho (almost sab kuch mar jaaye)?

M \geq \frac{N}{1 - f} \to \infty

, matlab tumhein essentially infinite cores chahiye honge — so wafer-scale tabhi sense karta hai jab

f

itna chhota ho ki

\frac{1}{1 - f}

ek modest over-provisioning factor rahe.

Kya hoga agar model ka working set total on-wafer SRAM se bada ho?

WSE apna advantage kho deta hai — on-wafer koi DRAM fallback nahi hai, so ek workload jo aggregate SRAM overflow kare woh ek aisa case hai jahan off-chip memory actually help karta.

Kya hoga agar traffic nearest-neighbor ki jagah corner-to-corner ho?

Latency ~thousands of hops (~µs) tak balloon kar jaati hai, so ek workload jo long-distance mesh traffic se dominated ho woh locality bet ko defeat karta hai jis par yeh architecture built hai.

Redundancy ke saath WSE ka effective yield metric kya hai, versus normal chip?

Ek normal chip ko zero killing defects chahiye (

Y = e^{- D A}

); ek WSE ko sirf 'enough good cores' chahiye, so scattered dead cores wala wafer abhi bhi ek fully usable product hai.

Kya hota hai power delivery ka agar tum current wafer edges se feed karne ki koshish karo?

~215 mm die ke across in-plane resistive path huge

I^{2} R

voltage drops aur heating cause karega, yahi wajah hai ki current back face se vertically feed ki jaati hai.

Recall Har trap ki ek-line summary

Yield math sirf perfect wafers ko kill karta hai, so WSEs redundancy use karte hain; koi DRAM nahi hai (SRAM sharded aur summed hai); bandwidth additive hai kyunki links parallel mein chalte hain; latency tab sasti hai jab traffic local ho; aur power vertically aati hai, edges se nahi.