Worked examples — Approximate computing techniques
6.5.16 · D3· Hardware › Advanced & Emerging Architectures › Approximate computing techniques
Scenario matrix
Is topic ka har problem inhi cells mein se ek hai. Is page ka goal hai: har cell ke liye ek worked example.
| # | Cell (case class) | Kya cheez ise alag banati hai | Covered by |
|---|---|---|---|
| C1 | Unbiased error, badi aggregation | errors mean-zero → relative error ki tarah shrink hota hai | Example 1 |
| C2 | Biased error, badi aggregation | errors sab ek hi sign ke → error ki tarah grow karta hai (trap) | Example 2 |
| C3 | Positive product ka truncation | LSBs drop karna → hamesha under-estimate (one-sided sign) | Example 3 |
| C4 | Rounding vs truncation | same bits rakhe, par symmetric error → aadhi magnitude | Example 4 |
| C5 | Precision-scaling energy ( law) | quadratic multiplier cost, degenerate | Example 5 |
| C6 | Voltage overscaling ( vs delay) | power win vs timing-error onset; limiting | Example 6 |
| C7 | Loop perforation, real image | word problem: speedup vs PSNR bound | Example 7 |
| C8 | Feedback / accumulation | tiny per-step error, par iterations ke saath amplify hota hai | Example 8 |
| C9 | Exam twist: exponent vs mantissa | GALAT field approximate karna → catastrophe | Example 9 |
| C10 | Zero / degenerate inputs | , error , bits — kya limits sahi behave karti hain? | Example 10 |
Compute karne se pehle, ek symbol ko pakka samajh lo, kyunki yeh neeche har jagah aata hai.
Example 1 — C1: badi sum par unbiased error
Steps.
- Total error . Iska variance hai . Yeh step kyun? Independent zero-mean errors variance mein add hote hain, magnitude mein nahi — parent note ka classic rule.
- Typical error size . Kyun? Standard deviation ; yahi "typical" spread hai.
- Signal (true sum) . Kyun? Error compare karne ke liye kuch chahiye — sum khud.
- Relative error .
Recall Verify
Agar ko quadruple karke karein: error , signal , relative — aadha ho gaya. Relative error ki tarah girta hai. ✅ Units: error aur signal dono "reading units" mein, ratio dimensionless hai. ✅
Example 2 — C2: biased trap
Steps.
- Bias linearly accumulate hota hai: . Yeh step kyun? Means directly add hote hain — jab sab ek sign share karte hain toh cancellation nahi hoti.
- Zero-mean part se compare karo, jo ( ke saath) sirf hai. Kyun? Dekho kaun sa term dominate karta hai. , ko daba deta hai.
- Relative error — 40× worse than Example 1, aur yeh ke saath badhta hi rehta hai, shrink nahi hota.
Recall Verify
Bias term (random term with ). ✅ par: bias ( ke saath bada), jabki random term sirf badhkar hua — confirm karta hai bias , random . ✅
Example 3 — C3: positive product truncate karna (one-sided sign)
Steps.
- Exact: . Kyun? Ground truth. , .
- Binary mein, (6 nonzero fractional bits). 4 fractional bits rakho: . Kyun? Truncation tail kaatta hai — hardware simply un partial-product columns ko omit karta hai.
- Error . Yeh hamesha hai: tumne positive weight remove kiya, isliye truncated result kabhi bhi true se bada nahi hota. Yeh kyun matter karta hai? Truncation ek biased approximation hai → yeh kaafi baar add hone par cell C2 ke danger family mein aata hai.
- Relative error .
Recall Verify
Dropped bits hain exactly. ✅ Error positive hai. ✅
Example 4 — C4: iske badle rounding karna (symmetric error)
Steps.
- Joh tail drop ho rahi hai woh hai , jo ek 4th-bit unit ke aadhe se zyada hai (; aadha hai ). Yeh step kyun? Rounding tail dekhta hai: agar aadha unit, toh upar round karo.
- Kyunki , upar round karo: . Kyun? Rounding nearest representable value ki taraf push karta hai, hamesha neeche nahi.
- Rounding error (ab negative — sign dono taraf ja sakta hai). Magnitude : truncation se 3× chhota.
Recall Verify
exactly. ✅ Sign negative hai (true value se upar round ho gaya). ✅
Example 5 — C5: precision-scaling energy, law
Steps.
- Ratio . kyun? Ek array multiplier full-adder cells tile karta hai; har cell energy burn karta hai → total area ke saath scale karta hai.
- Toh ek INT8 multiply FP32 mantissa multiply se lagbhag kam energy use karta hai. kyun, nahi? FP32 stored 32 bits hai, par 1 sign + 8 exponent bits mantissa multiplier mein enter nahi karte — sirf 24-bit significand multiply hota hai (dekho Precision and Number Formats (FP32, FP16, INT8)).
- Degenerate check. set karo: ratio . Yeh parent note ka "halving = 4×" reproduce karta hai. Kyun? law scale-free hai — sirf bit-widths ka ratio matter karta hai.
Recall Verify
, aur halving deta hai. Dono neeche check kiye. ✅
Example 6 — C6: voltage overscaling, win vs wall

Steps.
- Power ratio . kyun, nahi? Har switching node ek capacitor ko voltage tak charge karta hai, energy store karta hai — square physics hai, choice nahi.
- Savings . Care kyun? 20% voltage drop 36% power cut deta hai — " jackpot."
- Par risk ( term): gate delay badhta hai jaise . V par: delay factor . par: . par: → slower. Kuch paths ab clock miss karte hain → timing errors. Yeh kyun matter karta hai? Figure par, green power curve smoothly girta hai jabki red delay curve ke paas shoot up karta hai — yahi error cliff hai. VOS safe point se thoda left par, par cliff se right par rehta hai.
Recall Verify
Power save . Delay ratio . ✅
Example 7 — C7: loop perforation, real image (word problem)
Steps.
- Speedup: hum aadhi rows skip karte hain → kam iterations ⇒ ~2× faster. Acceptable kyun? Natural images mein adjacent rows highly correlated hoti hain (redundancy → C1-style resilience).
- PSNR dB. Yeh formula kyun? Yeh page ke upar se quality ruler hai — MAX over MSE.
- ✅ — perforation-by-2 just pass karta hai. Perforate-by-4 push karo aur MSE roughly quadruple hoti hai, PSNR dB drop karta hai → fail. par dB kyun? ; MSE quadruple hone par dB subtract hota hai.
Recall Verify
dB (2 dp tak). ✅ MSE pe dB lagti hai. ✅
Example 8 — C8: feedback loop mein error accumulation
Steps.
- Recursion solve karo: ke saath, (geometric series). Yeh step kyun? Feedback past errors ko har round mein se multiply karta hai — closed form growth expose karta hai.
- Plug in karo: . Kyunki , . Alarming kyun? Ek per-step error ban gaya — amplify hua.
- Contrast ke saath (koi amplification nahi): . Same per-step error, 28× chhota. Kyun? Jab hota hai loop unstable hota hai aur errors compound hote hain; /linear intuitions APPLY NAHI HOTI.
Recall Verify
, vs giving . Ratio . ✅
Example 9 — C9: exam twist — SAHI field approximate karo
Steps.
- Mantissa LSB flip. FP16 mantissa mein 10 bits hain; LSB mantissa ka worth hai. Naya value . Relative error . Chhota kyun? Mantissa sirf fine detail set karta hai — yahi woh LSB hai jise hum approximate kar sakte hain.
- Exponent flip (maan lo high exponent bit flip karke): value . Yeh zyada bada hai — magnitude destroy ho gayi. Catastrophic kyun? Exponent scale control karta hai; ek galat bit poore number ko power of two se multiply karta hai.
- Rule. Mantissa LSBs aur pixel data approximate karo; kabhi nahi exponents, pointers, loop bounds, ya control flow. Un critical bits ko Error-Correcting Codes se protect karo. Kyun? Mantissa slip ek nuisance hai; exponent slip ek (ya worse) disaster hai — dono completely alag scales par rehte hain, isliye tum kaun sa field approximate karte ho yeh matter karta hai zyada, na ki kitne bits touch karte ho.
Recall Verify
Mantissa flip: , relative . ✅ Exponent flip : ratio . ✅
Example 10 — C10: zero & degenerate limits (sanity boundary)
Steps.
- (koi aggregation nahi). Relative error — poora single-op error, koi rescue nahi. ke saath: . Kyun? Aggregation ko bahut saare terms chahiye; ek term kuch cancel nahi karta. shrink sirf ke liye help karna shuru karta hai.
- Error (exact op). Tab → relative error sab ke liye. Exact machine approximate machine ka limit hai — consistent, koi discontinuity nahi. Check kyun? Ek approximate model ko exact model reduce ho jaana chahiye jab tum error zero par dial karo.
- bits (degenerate precision). Multiplier energy : zero bits ⇒ zero hardware ⇒ zero energy aur zero information. law cleanly par trivial machine par limit karta hai. Check kyun? Ek achha formula apni boundary par explode ya contradict nahi karna chahiye.
Recall Verify
: . : relative . : . Sab finite/consistent hain. ✅
Recall Pure matrix ki one-line summary
Unbiased+aggregated error shrink hota hai (); biased error drift karta hai (); truncation biased hai, rounding (almost) unbiased aur aadhi size; multiplier energy scale karta hai; voltage bachata hai par ke paas delay wall se takraata hai; wala feedback amplify karta hai; kabhi bhi exponents/control mat chhuona.