Question bank — Approximate computing techniques

False. Error engineered aur bounded hai — hum exactly choose karte hain kahan jaati hai (LSBs, non-critical data) aur ek quality guarantee prove karte hain; yeh ek design knob hai, defect nahi.

False. Ek $n\times n$ array multiplier $\approx n^2$ full-adder cells layout karta hai (ek square grid — figure s03 dekho), toh energy $\propto n^2$; $n$ half karne se $(1/2{)}^2=1/4$ milta hai — ek 4× cut, 2× nahi. Dekho Ripple-Carry vs Array Multipliers.

False. Dynamic power $\propto V^2$, toh $1-0.8^2=0.36$ → lagbhag 36% saving. Square (figure s01) exactly isliye voltage overscaling ek jackpot hai. Dekho Dynamic Power P = alpha C V^2 f.

True. Total error $\sqrt{N}\sigma$ ki tarah badhti hai jabki sum $N\mu$ ki tarah badhta hai, toh ratio $\sim \sigma /(\mu \sqrt{N})\to 0$ hota hai (figure s04 mein histogram dikhata hai ki error pile-up narrow rehta hai).

False. Yeh sirf tab cancel hoti hai jab errors independent aur zero-mean hoon; ek biased scheme (jaise hamesha downward truncate karna) systematically drift karta hai aur $\sqrt{N}$ nahi balki $N$ ki tarah badhta hai (figure s04 mein dono lines diverge karti hain).

False. Precision scaling circuit ko shrink karta hai (kam switching cells, $C$ mein $n$ ya $n^2$ factor); overscaling same circuit rakhte hue $V^2$ term ko shrink karta hai. $P=\alpha C{V}^{2}f$ pe alag-alag levers hain.

False. Yeh ulti wajah se kaam karta hai — adjacent rows/pixels highly correlated hote hain, toh skipped row ko uske neighbour se achhi tarah approximate kiya ja sakta hai.

False. $n^2$ multiplier shrinkage sabse bada single factor hai (figure s05), lekin INT8 saath hi 4× kam bytes move karta hai → kam memory-bandwidth aur data-movement energy; ek naive kernel jo abhi bhi FP32-sized data shuffle karta hai win ka zyada hissa gawa sakta hai. Arithmetic aur data movement dono matter karte hain. Dekho Neural Network Quantization.

True. Kam refreshes power bachate hain lekin kuch cells decay hone aur flip hone dete hain; agar data error-tolerant hai (jaise pixel values), woh flips acceptable hain. Dekho DRAM Refresh and Memory Reliability.

True. Truncation hamesha tail drop karta hai (zero ki taraf round karta hai), toh error ka consistent sign hota hai — yahi bias wajah hai ki rounding schemes aggregation ke liye often preferred hote hain (figure s04 mein drifting line dekho).

Error hai control flow / addresses ko approximate karna — loop bounds ya pointers corrupt karne se crashes ya wild output hoti hai; sirf tolerant data ko approximate kiya ja sakta hai.

Exponent magnitude control karta hai; ek galat exponent bit kisi value ko power of two se multiply kar sakta hai → catastrophic error. Sirf mantissa LSBs safe hain. Dekho Precision and Number Formats (FP32, FP16, INT8).

Opposite goals — Error-Correcting Codes extra bits/energy kharach karte hain error hatane ke liye, approximate memory error allow karti hai energy bachane ke liye. Ek use karo jahan reliability matter karti hai, doosra jahan nahi karta.

$\sqrt{N}$ law independent errors ko sum pe assume karta hai. Feedback loop mein errors step-to-step amplify ho sakti hain; tumhe stability check karni padegi, sirf per-op error nahi.

Delay $V$ girne ke saath badhti hai ($t_d\propto V/(V-V_{th}{)}^{\beta }$, figure s01 mein steep curve); fixed clock pe kuch paths apni deadline miss karte hain → timing errors. Yeh sirf isliye "kaam karta hai" kyunki woh errors non-critical LSBs pe steer ki jaati hain.

Ulta hai — PSNR ek quality metric hai log scale pe, higher better hai. 41 dB cleaner image hai; $+8$ dB gap ka matlab hai kai-guna kam error (figure s02).

Guaranteed nahi — per-op error aur end-to-end quality alag quantities hain; errors accumulate, cancel, ya amplify ho sakti hain algorithm ke hisaab se. Tumhe application metric (PSNR, accuracy) measure karna hoga.

Ek $n$-bit ripple adder $n$ full-adders ki ek line hai → energy $\propto n$. Ek $n\times n$ array multiplier $\approx n^2$ full-adders ka ek square grid hai (figure s03) → energy $\propto n^2$. Kyunki grid do directions mein badhta hai, $n$ shrink karna area ko quadratically remove karta hai — woh quadratic hi lever hai. Dekho Ripple-Carry vs Array Multipliers.

(1) Koi bhi input worst case ho sakta hai. (2) Jo system tum ship karte ho use sabhi inputs pe quality promise karni hoti hai. (3) Toh tumhe error ka proven ceiling chahiye, average nahi — ek unbounded scheme kisi rare input pe silently fail kar sakta hai chahe woh usually theek ho.

(1) Rounding errors roughly zero-mean hote hain, toh $N$ unhe sum karne pe $+$ aur $-$ cancel hote hain → total sirf $\sqrt{N}$ ki tarah badhta hai. (2) Truncation hamesha ek taraf lean karta hai (bias), toh uski errors add up hoti hain → total $N$ ki tarah badhta hai. (3) Bade $N$ ke liye biased line unbiased wali ke upar tower karti hai (figure s04) — same per-op size, wildly different totals.

(1) Reward: power $V^2$ ki tarah girta hai, toh thodi si voltage cut se disproportionate power cut milta hai (left curve, figure s01). (2) Risk: delay $t_d\propto V/(V-V_{th}{)}^{\beta }$ jab $V\to V_{th}$ hota hai toh blow up karta hai (right curve). (3) Dono race karte hain: gains sirf tab risks se aage rehte hain jab induced timing errors saste-se-tolerate LSBs pe land karti hain.

(1) Tum thermal/power budget ke andar saare transistors ek saath power nahi kar sakte. (2) Approximation per useful result energy cut karta hai. (3) Toh same power budget zyada useful compute khareedta hai — approximation directly "dark" area wapas khareedta hai. Dekho Dark Silicon and Energy-Efficient Architectures.

(1) Har output kaafi weighted inputs ka sum hai — ek aggregation, toh per-multiply noise partly cancel hoti hai ($\sqrt{N}$ law). (2) Final answer ek discrete decision hai ("cat"), score mein choti tharakhanon ke liye robust hai. (3) Result: chhoti multiply errors rarely class flip karti hain. Dekho Neural Network Quantization.

(1) Bit-width $n$ sirf kitne bits hain yeh fix karta hai. (2) Circuit design decide karta hai woh bits kaise behave karein — exact vs approximate full-adder, array kahaan truncate hota hai, voltage kitna overscale hota hai. (3) Same $n$, alag engineering ⇒ alag error.

$N=1$ ke saath cancel karne ke liye kuch nahi hota — $\sqrt{N}$ shrinkage gayab ho jaata hai aur relative error poori $\sigma /\mu$ hoti hai. Ek akela approximate op ko apne dum pe tolerate karna padta hai, statistics se nahi.

Woh cancel karna band kar dete hain; sum ke variance mein positive cross-terms aa jaate hain aur $N$ ki jagah $N^2$ ki tarah badh sakta hai, toh standard deviation $N$ ki tarah badhti hai — $\sqrt{N}$ benefit bilkul khatam ho jaata hai (yeh figure s04 mein biased curve ka cousin hai).

Ek degenerate, dangerous case — ek corrupted index/branch "thoda sa galat output" nahi hai balki out-of-bounds access, crash, ya arbitrary jump hai. Aisa data strictly off-limits hai, chahe kitni bhi energy bachti ho.

Sabse lamba (critical) timing path pehle fail hota hai — uske paas sabse kam slack hota hai, aur figure s01 ki delay curve wahan sabse tezi se rise karti hai. Jab $V$ aur girta hai, errors LSBs se upar MSBs ki taraf creep karne lagte hain jab tak quality bound break na ho jaaye aur output garbage na ban jaaye.

Yeh har iteration skip karta hai — ek degenerate case jo koi real kaam nahi karta; output pure copy/interpolation hai initial state ka. Speed-vs-quality trade-off collapse ho gaya hai aur quality unbounded (useless) hai.

Essentially kuch nahi — har bit critical hai (ek single flipped ledger cent ya cipher bit ek hard failure hai), toh error inject karne ki koi safe jagah nahi hai. Yeh technique simply apply nahi hoti.