6.5.5 · D4 · HinglishAdvanced & Emerging Architectures

ExercisesProcessing-in-memory (PIM)

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6.5.5 · D4 · Hardware › Advanced & Emerging Architectures › Processing-in-memory (PIM)

Shuru karne se pehle, yeh chhota sa toolbox hai jisse har problem draw karti hai. Ise saamne rakhein.

Figure — Processing-in-memory (PIM)

Upar wali figure hamaara map hai: roofline. Left mein flat part bandwidth-bound territory hai (PIM ka home turf); right mein slanted part compute-bound hai (caches aur fast ALUs jeette hain). Arithmetic intensity har workload ko left-to-right place karta hai.


L1 — Recognition

Exercise 1.1

Ek job mein operations hain aur bytes move hote hain. Arithmetic intensity compute karo aur ek word mein batao ki yeh bandwidth-bound hai ya compute-bound.

Recall Solution 1.1

KYA karte hain: definition apply karo. KYUN yeh question ka jawab deta hai: hai "har fetched byte par kitna math." Quarter-op per byte matlab hai ki har single operation ke liye hum chaar bytes fetch karte hain — wire almost saara kaam karta hai. Verdict: bahut low bandwidth-bound ⇒ ek acha PIM candidate.

Exercise 1.2

PIM ke do flavors define kiye gaye the. Kaun sa flavor array ki khud ki analog physics (jaise memristor crossbar) use karta hai, aur kaun sa ordinary digital logic ko memory ke physically paas rakhta hai?

Recall Solution 1.2
  • Processing-using-memory (PUM): memory ki apni physics use karke compute karta hai — woh crossbar jahan Ohm's + Kirchhoff's laws ek matrix–vector multiply karte hain. Dekho Memristor / ReRAM Crossbars.
  • Processing-near-memory (PNM): ordinary ALUs/cores jo memory ke side mein rakhe hote hain, jaise ek 3D-stacked HBM stack ke logic die par. Parent se mnemonic: Near = Next to; Using = memory ki apni physics.

Exercise 1.3

True ya false: "PIM ki main win ek faster ALU hai." Ek sentence mein justify karo.

Recall Solution 1.3

False. PIM ki win reduced data movement hai, faster arithmetic nahi — yeh Memory Wall par attack karta hai, jo bus ke across bytes khींchne ki cost hai. (Yahi woh trap hai jo steel-manned just below hai.)


L2 — Application

Exercise 2.1

Ek vector operation a[i] = 2*b[i] + c[i] elements ke upar run karta hai jo 4-byte floats hain. Har element ko ek multiply aur ek add chahiye. , , aur compute karo.

Recall Solution 2.1

KYA — ops count karo: har element mein ek multiply + ek add ⇒ ops each. KYUN: operation 2*b[i] + c[i] literally ek multiplication aur ek addition spell out karta hai, aur hum ise elements mein se har ek ke liye perform karte hain — toh op count simply per element times elements hai. KYA — bytes count karo: b read karo, c read karo, a write karo ⇒ 3 accesses × 4 bytes each. KYUN: har memory touch bus cross karta hai aur count hona chahiye — do reads (b, c) plus ek write (a) per element, har ek 4-byte float. Write-back bhool jaana classic slip hai (neeche trap dekho). KYA — intensity: KYUN matters hai: bahut chhota hai — hum har op ke liye chhe bytes move karte hain. Roofline par (figure s01) yeh flat, bandwidth-bound zone mein bahut left land karta hai ⇒ acha PIM candidate.

Exercise 2.2

Ek HBM stack mein banks hain, har ek ka internal bandwidth GB/s hai. External bus GB/s hai. Near-memory speedup estimate karo.

Recall Solution 2.2

KYA — internal bandwidth: KYUN: banks mein se har ek apne data ko simultaneously read aur compute karta hai; kyunki woh parallel mein run karte hain, unke bandwidths add hote hain. Yahi internal parallelism woh resource hai jo external bus kabhi expose nahi kar sakta. KYA — speedup (bandwidth-bound approximation): KYUN yeh ratio: bandwidth-bound job ke liye runtime set hota hai ki bytes kitni tezi se flow karte hain. PIM GB/s wire ko GB/s internal flow se replace karta hai, toh time bandwidth ratio se shrink hota hai — yahan . (Jab compute time negligible nahi hoti tab yeh over-estimate karta hai; full timing jo gap expose karta hai woh Exercise 5.2 mein hai.)

Exercise 2.3

Rough energy fact: operands move karne ki cost hai, jahan ek op ki energy hai. ops/byte wale job ke liye, roughly kitna fraction energy data move karne mein jaata hai vs. computing mein? (Assume karo ek "move event" per byte, ek per op.)

Recall Solution 2.3

KYA hum build karte hain: per byte hum ops karte hain, toh per byte:

  • compute energy
  • move energy

KYUN per byte split karo: "per byte moved" normalize karna dono energies ko same footing par compare karne deta hai — ek move event (cost ) against woh fraction of op jo woh byte earn karta hai (). Moving ka fraction: Interpretation: essentially saari energy data move karne mein jaati hai. Yahi wajah hai PIM exist karta hai — movement cut karo aur aap almost poora energy bill cut kar dete ho.


L3 — Analysis

Exercise 3.1

size ka ek dense matrix multiply karne mein ops aur bytes move hote hain. compute karo aur decide karo: kya PIM yahan strong win hai? Exercise 2.1 ke vector add se contrast karo.

Recall Solution 3.1

Ops: . Bytes: . Intensity: Analysis: vector add ke ke comparison mein bahut bada hai. Matrix multiply har loaded value ko times reuse karta hai, toh yeh compute-bound hai — caches aur fast ALUs already ise feed karte rehte hain. PIM ka bandwidth win barely apply hota hai. Dekho Roofline Model.

Exercise 3.2

Ek workload 70% bandwidth-bound hai (is fraction ko kahein) aur PIM us part ko faster banata hai. Baaki 30% untouched hai. Amdahl's Law use karke overall speedup compute karo.

Recall Solution 3.2

Amdahl's Law: agar runtime ka ek fraction ko se speed up kiya jaye, aur baaki () unchanged rahe, toh overall speedup hai KYUN yeh tool: PIM sirf job ke movement part ko accelerate karta hai; baaki ek serial anchor hai. Amdahl exactly "kya hota hai jab aap sirf ek slice speed up karo" wala sawaal hai. Plug in : 4× local win bhi sirf ~2.1× overall deta hai — untouched 30% aapko cap karta hai.

Exercise 3.3

Aap measure karte ho ki PIM 3.2 wale job ke liye hone par bhi maximum possible speedup ke near deta hai. Woh ceiling kya hai, aur yeh kya prove karta hai?

Recall Solution 3.3

Amdahl mein let karo: term ho jaata hai, yeh bachta hai: Proof it delivers: chahe PIM kitna bhi acha ho jaye, serial 30% aapko 3.33× par cap karta hai. Isliye bandwidth-bound fraction measure karna tune karne se zyada matter karta hai — ceiling mein rehti hai.


L4 — Synthesis

Exercise 4.1

Ek memristor crossbar mein size ki matrix hai jahan . Input voltages hain volts. Row current produce karta hai (Ohm's law per cell, Kirchhoff's sum per row). Diya gaya hai output current vector compute karo. Phir batao ki yeh kitne analog steps mein hua vs. ek sequential CPU.

Recall Solution 4.1

Symbol note: yahan (boldface, components ) ek electric current vector hai — nahi pehle wale problems ki arithmetic intensity . Same letter, alag duniya; boldface aur "amps" units dono ko alag rakhte hain. KYUN crossbar yeh ek shot mein karta hai: har crosspoint Ohm's law follow karta hai; shared row wire par currents add hote hain (Kirchhoff), jisse milta hai — ek dot product per row, saari rows parallel mein. Neeche figure s02 mein trace karo: input voltages (lavender arrows) columns ke neeche enter karte hain, har crosspoint conductance (coral dots) apni column ki voltage ko current mein scale karta hai, aur currents har mint row wire ke saath rightward merge hote hain output (coral arrows) mein. Row by row ():

Step count: crossbar yeh ek analog step mein karta hai (). Ek CPU ko multiply-accumulates chahiye (). Woh collapse isliye hai kyun PIM Neural Network Accelerators ko love karta hai.

Figure — Processing-in-memory (PIM)

Is figure ko Solution 4.1 ke saath padhein: yeh numbers ke peeche ki physical picture hai. Har coral dot ke andar printed conductance corresponding matrix se hai; ise apne column ki voltage se multiply karo aur row ke along sum karo taaki har haath se reproduce ho sake.

Exercise 4.2

Do levels combine karo. Ek neural-net layer 90% matrix–vector multiply hai runtime se (). Ek crossbar woh part effectively faster karta hai. (a) Amdahl se overall speedup? (b) Lekin crossbar output approximate hai (device drift, ADC noise). Workload ki kaun si class yeh acceptable banati hai, aur kya cheez ise unacceptable banayegi?

Recall Solution 4.2

(a) Amdahl with : (b) Error-tolerant workloads ke liye acceptable hai — neural network inference chhote numeric noise tolerate karta hai (training ne already robustness add ki hai). Unacceptable exact workloads ke liye jaise IEEE-precise finance ya cryptography, jahan ek drifted conductance result corrupt kar deta hai. PUM exactness ko speed ke liye trade karta hai.


L5 — Mastery

Exercise 5.1 (Design & defend)

Aapko teen workloads diye gaye hain. Har ek ke liye decide karo PUM crossbar, PNM (near-memory ALUs), ya plain CPU/GPU, aur numbers ke saath justify karo.

  • W1: streaming vector add, ops/byte, bit-exact hona chahiye.
  • W2: neural-net inference, matrix–vector multiplies se dominated, ~1% error tolerate karta hai.
  • W3: dense scientific matrix multiply, ops/byte, IEEE-exact hona chahiye.
Recall Solution 5.1

W1 → PNM. Bahut low ⇒ bandwidth-bound ⇒ PIM helps. Lekin yeh exact hona chahiye, toh hum analog PUM (approximate) use nahi kar sakte. Digital near-memory ALUs bandwidth win aur exactness dono dete hain. W2 → PUM crossbar. Matrix–vector multiply crossbar ka native operation hai; 1% error tolerance analog imprecision suit karta hai. Ideal PUM case. W3 → plain CPU/GPU. compute-bound, toh bytes already caches ke andar heavily reuse ho rahe hain aur PIM ka bandwidth win barely helps karta hai. Upar se job IEEE-exact honi chahiye, jo analog PUM ko poori tarah rule out karta hai. Ise GPU par rakhein, jahan cache se fed fast ALUs exactly sahi tool hain. Dekho Roofline Model.

Exercise 5.2 (Full pipeline estimate)

Ek job bytes move karta hai aur ops karta hai. External bus GB/s B/s. Compute rate ops/s. Ek PNM design mein banks hain, GB/s, aur same rate par compute execute karta hai. (a) Baseline time . (b) PIM time . (c) Actual speedup . Ise naive se compare karo aur gap explain karo.

Recall Solution 5.2

Internal bandwidth: GB/s B/s. (a) Baseline: (b) PIM: (c) Actual speedup: Naive estimate . Gap explained: naive ratio assume karta hai ki job pure movement hai. Yahan compute term s bada hai aur PIM se unchanged — woh naya bottleneck ban jaata hai. Yahi exactly Amdahl's ceiling hai: PIM ne sirf s movement part shrink kiya, s compute part nahi. Hamesha poora compute karo, kabhi par alone trust mat karo.


Wrap-up

the parent PIM note par wapas jao · related: DRAM Organization (banks, rows), Roofline Model, Amdahl's Law.