PCIe lanes, links, and bandwidth — Hinglish notes

6.3.3 · Hardware › Interconnects, Buses & SoC

Overview

PCIe lanes, links, aur unka bandwidth se relationship samajhna system design ke liye fundamental hai—chahe aap gaming rig bana rahe ho, server, ya debug kar rahe ho ki aapki NVMe drive advertised speed kyun nahi pakad rahi. Yeh note bandwidth ko first principles se derive karta hai aur dikhata hai ki aap kabhi confuse na ho.

Figure — PCIe lanes, links, and bandwidth

Core Concepts

Bandwidth Derivation from First Principles

Chaliye bandwidth formula ko step by step build karte hain, samajhte hain ki har component ka MATLAB kya hai aur WHY woh wahan hai.

Formula Step 1: Raw Bit Rate (Transfer Rate)

Har PCIe generation ek raw signaling rate define karta hai jis par bits wire par toggle karte hain:

Generation	Raw Bit Rate per Lane	Why This Speed?
PCIe 1.0	2.5 GT/s	Initial standard
PCIe 2.0	5.0 GT/s	2× clock rate
PCIe 3.0	8.0 GT/s	Improved encoding
PCIe 4.0	16.0 GT/s	2× Gen 3
PCIe 5.0	32.0 GT/s	2× Gen 4
GT/s GigaTransfers per second (abhi gigabits nahi—humne encoding overhead account nahi kiya hai).

WHY har generation mein speed exactly double nahi hoti? Gen 1→2 simple frequency doubling tha. Gen 2→3 mein encoding scheme badli (next step dekhein), jisne math affect kiya. Gen 3→4→5 mein wapas 2× jumps aaye.

Master Bandwidth Table

| Gen | Encoding | Lane Rate (Gbps) | Lane Rate (GB/s) | x1 | x4 | x8 | x16 (GB/s) | |-----|----------|------------------|---------------|----|----|----| | 1.0 | 8b/10b | 2.5 × 0.8 = 2.0 | 0.25 | 0.25 | 1.0 | 2.0 | 4.0 | | 2.0 | 8b/10b | 5.0 × 0.8 = 4.0 | 0.5 | 0.5 | 2.0 | 4.0 | 8.0 | | 3.0 | 128b/130b| 8.0 × 0.985 = 7.88| 0.985 | 0.985| 3.94| 7.88| 15.75 | | 4.0 | 128b/130b| 16.0 × 0.985 = 15.75| 1.969 | 1.969| 7.88| 15.75| 31.51 | | 5.0 | 128b/130b| 32.0 × 0.985 = 31.51| 3.938 | 3.938|15.75| 31.51| 63.02 |

Saari values unidirectional (one-way) bandwidth hain.

Common Mistakes & Misconceptions

Recall Ek 12-Saal Ke Bachche Ko Samjhao

Socho tum apne dost ko paper airplanes se messages bhej rahe ho. Har airplane ek PCIe lane ki tarah hai.

Ek lane (x1): Tum ek airplane fold karte ho, message likhte ho, aur phekte ho. Tumhara dost ek wapas fold karta hai. Tum dono ek saath phek rahe ho (yahi full-duplex hai). Tum shayad 1 message per second bhej sakte ho. 16 lanes (x16): Ab tumhare paas 16 dost hain, har ek ke paas apna airplane hai. Saare 16 ek saath phekte hain, saare 16 ek saath receive karte hain. Tum per second 16× zyada messages bhej rahe ho—yahi zyada bandwidth hai.

Encoding: Tumhara kuch message actual content hai (data), lekin tum upar "Message #5" bhi likhte ho taaki tumhare dost ko order pata chale. Woh overhead hai—saare paper mein useful content nahi hoti.

Generations: PCIe 1.0 slowly phekne jaisa hai (2.5 messages/second per airplane). PCIe 5.0 bahut tezi se phekne jaisa hai (32 messages/second per airplane). Har generation phekne mein tezi se improve hoti hai.

Yeh kyun matters hai: Agar tum game khel rahe ho, tumhara graphics card (GPU) computer ki memory se BAHUT saare messages bahut tezi se chahiye—jaise ek dragon ke textures. Zyada lanes aur faster generations = smoother dragon kyunki messages time par pahunch jaate hain.

Connections

PCIe Architecture Overview — Lanes layered PCIe protocol stack ka part hain
PCIe Electrical Signaling — Differential pairs, lanes physically bits kaise transmit karti hain
NVMe Protocol — PCIe lanes ko apni transport layer ki tarah use karta hai
8b10b Encoding — Gen 1-2 encoding overhead ki detailed look
128b130b Encoding — Gen 3+ zyada efficient kyun hai
Motherboard Lane Allocation — CPU aur chipset lanes kaise distribute karte hain
GPU Bandwidth Requirements — GPUs ko x16 lanes kyun chahiye
PCIe Bifurcation — x16 ko multiple smaller links mein split karna

#flashcards/hardware

PCIe lane kya hota hai? :: Ek full-duplex serial connection jo do differential pairs se bana hota hai—ek TX pair (device se host) aur ek RX pair (host se device). Data dono directions mein simultaneously flow karta hai.

PCIe link kya hota hai?

Ek ya zyada lanes ka physical connection bundled together. Common widths x1, x4, x8, aur x16 hain.

PCIe Gen 1 aur 2 kaunsa encoding use karte hain, aur efficiency kya hai?

8b/10b encoding 80% efficiency ke saath (10 transmitted bits mein 8 data bits).

PCIe Gen 3, 4, aur 5 kaunsa encoding use karte hain, aur efficiency kya hai? :: 128b/130b encoding approximately 98.46% efficiency ke saath (130 transmitted bits mein 128 data bits).

PCIe data rate per lane ka formula kya hai?

Data Rate (Gbps) = Raw Rate (GT/s) × Encoding Efficiency. Phir GB/s mein convert karne ke liye 8 se divide karo.

PCIe 3.0 x16 ki unidirectional bandwidth kya hai?

Approximately 15.75 GB/s (8.0 GT/s × 128/130 × 16 lanes ÷ 8 bits/byte).

PCIe 4.0 x4 ki unidirectional bandwidth kya hai?

Approximately 7.88 GB/s (16.0 GT/s × 128/130 × 4 lanes ÷ 8 bits/byte).

PCIe 3.0 slot mein PCIe 4.0 device slower kyun run karta hai?

PCIe lowest common generation par negotiate karta hai. Device PCIe 3.0 speeds par operate karega (4.0 ki half bandwidth) chahe woh zyada capable ho.

PCIe context mein bifurcation ka matlab kya hai?

Ek physical x16 slot ko multiple independent links mein split karna (e.g., x8/x8 ya x4/x4/x4/x4) taaki multiple devices connect ho sakein.

Unidirectional aur aggregate bandwidth mein kya fark hai?

Unidirectional ek direction (TX ya RX) mein bandwidth hai. Aggregate dono directions ka sum hai. Kyunki PCIe full-duplex hai, aggregate = 2 × unidirectional.

PCIe 5.0 ki raw signaling rate (GT/s) kya hai?

32.0 GT/s per lane.

PCIe ne Gen 3 par 8b/10b se 128b/130b encoding kyun switch kiya?

Encoding overhead 20% se ~1.5% tak reduce karne ke liye. Zyada speeds par, 8b/10b ka wasted bandwidth bahut expensive ho gaya tha, jisse zyada complex 128b/130b encoding worthwhile ho gayi.