6.2.1 · D1GPU vs CPU design philosophy
Intuition Is poore topic ke peeche ek hi idea haiEk CPU aur ek GPU dono arithmetic karte hain, lekin woh alag sawaalon ke jawaab dete hain: CPU poochta hai "main ek kaam kitni jaldi khatam kar sakta hoon?" jabki GPU poochta hai "main har second kitne kaam khatam kar sakta hoon?" Neeche har ek symbol — latency, throughput, cores, transistor budgets, warps — sirf usi ek trade-off ko precise aur measurable banana ke liye exist karta hai.
Pehle aapko GPU vs CPU design philosophy padhna hai to aapko page par har ek mark padhna aana chahiye. Yeh note har ek symbol, term, aur picture ko jo parent use karta hai, zero se build karta hai. Upar se neeche padho; har block sirf wahi words use karta hai jo uske upar define hue hain.
Sab kuch ek word se shuru hota hai: ek task . Ek task kaam ka ek self-contained tukda hai — ek pixel ko colour karo, do numbers compare karo, do floats add karo.
Ek machine tasks mein kitni achi hai yeh measure karne ke do bilkul alag tarike hain. Inhe confuse karna is topic ki sabse badi galti hai, isliye pehle dono pictures build karte hain.
Latency woh time hai jab se ek task shuru hota hai jab tak wahi same task khatam hota hai. Socho ek stopwatch jo aap tab start karte ho jab runner blocks chhod ta hai aur tab stop karte ho jab woh line cross karta hai. Chhoti latency = woh ek kaam jaldi khatam hua.
Throughput woh tasks ki sankhya hai jo time ki ek unit mein khatam hote hain — ek rate , duration nahi. Socho finish line par khade ho aur count kar rahe ho ki kitne runners har minute cross karte hain, yeh ignore karte hue ki koi ek runner kitna time liya. Bada throughput = har second zyada kaam ho rahe hain.
Intuition Hume DONO kyun chahiyeEk factory mein conveyor belt ki high latency ho sakti hai (har item ko belt par travel karne mein 10 minute lagte hain) phir bhi high throughput ho sakta hai (ek khatam hua item har second neeche girta hai, kyunki belt par ek saath 600 items hain). Low latency ka matlab high throughput nahi, aur vice-versa. Parent note ki poori argument yeh hai: CPUs low latency ke peeche bhagte hain, GPUs high throughput ke peeche.
Topic ko alag do words ki zaroorat kyun hai? Kyunki ek design choice jo ek ko help kare doosre ko hurt kar sakti hai. Agar aapke paas do naam na hote, "GPU slower hai lekin faster bhi hai" nonsense lagta — do namon ke saath yeh "higher latency, higher throughput" ban jaata hai, jo bilkul sach hai.
Parent note formulas mein letters bharta hai. Har letter bas ek count ya rate hai. Yeh poora alphabet hai jo aapko chahiye.
Definition Counting symbols
N ek count — ek plain whole number. N instructions N tasks N cores P parallel processors ki sankhya (workers ek saath kaam kar rahe hain). P N cores P parallelism par stress karna chahta ho.t EK cheez ka time . t inst t task T total time . Units: seconds.f clock clock frequency = chip har second kitne steps leta hai, GHz mein measure kiya (billions per second).
T = P N × t task N = 12 t task = 30 P = 3 N / P = 4 3 12 × 30 = 120 workers mein kaam divide karta hai ; × t task
Topic mein yahan division kyun chahiye, subtraction nahi? Kyunki zyada workers add karna pile ko split karta hai — ek multiplicative/ratio effect — koi fixed discount nahi. Division hi woh akela operation hai jo "pile ko barabar baanto" ko capture karta hai.
CPU model T C P U = I P C × f clock N instructions
Definition Cycle, clock frequency, aur IPC
Ek cycle chip ki internal clock ki ek tick hai — processor ki sabse chhoti heartbeat.
f clock IPC = Instructions Per Cycle = chip ek tick ke dauran kitne instructions khatam karta hai. Agar IPC = 4 hai, chip har heartbeat mein 4 instructions retire karta hai.
Topic ko IPC ki parwah kyun hai? Kyunki parent ka central claim yeh hai ki ek CPU apne zyaadatar transistors sirf ek thread par IPC zyada karne ke liye kharach karta hai. Agar aap nahi jaante IPC ka matlab kya hai, toh "control logic exists to maximize IPC" ek khaali sentence hogi.
Parent CPUs aur GPUs ke liye "transistor budgets" deta hai. Aapko teen ideas chahiye: transistor, die, aur budget.
Definition Transistor, die, budget
Ek transistor chip par sabse chhota switch hai — digital hardware ka atom. Billions of them wire karke sab kuch banta hai.
Die silicon ka woh single flat rectangle hai jis se chip taraasha jaata hai. Iska fixed area hota hai.Ek transistor budget B fixed hai — ek feature par transistors kharach karne ka matlab hai doosre ke liye kam.
Intuition Budget ek pie hai jise aapko slice karna haiB compute (units jo arithmetic karte hain), cache (fast local memory), aur control (logic jo branches predict karta hai, instructions reorder karta hai). Ek CPU bade cache + control wedges aur chhota compute wedge kaatta hai. Ek GPU bada compute wedge aur tiny cache/control wedges kaatta hai. Same pie, ulti slicing — yahi design philosophy ek picture mein hai.
Cache fast memory ka ek chhota pool hai jo compute units ke bilkul paas hota hai, recently-used data ki copies rakhta hai taaki chip ko main memory (DRAM) tak lambi doori na karni pade. CPUs teen levels stack karte hain — L1 (sabse chhota, sabse fast), L2, L3 (sabse bada, shared).
Parent ka arithmetic 36.5 × 1 0 6 × 8 × 6 megabytes → bits → transistors . Ek byte = 8 bits, aur ek SRAM cache cell ko per bit lagbhag 6 transistors chahiye. Toh "36.5 MB cache kitne transistors cost karta hai?" = megabytes × 8 × 6. Kuch bhi mysterious nahi — yeh unit conversion hai.
Parent saare workloads ko do types mein baanta hai. Yeh distinction decide karta hai ki GPU ka "pile baanto" trick kaam bhi karega ya nahi.
Definition Data dependencyDo tasks mein data dependency hoti hai jab ek ko shuru hone se pehle doosre ka jawaab chahiye . Likhte hain I n I n − 1 n n − 1
Definition Embarrassingly parallelEk workload embarrassingly parallel hota hai jab tasks mein koi bhi dependencies nahi hoti — har ek complete isolation mein chal sakta hai. Pixel ( x 1 , y 1 ) ( x 2 , y 2 ) ideal case hai, kyunki aap jitne chahein utne workers use kar sakte ho.
Common mistake Parallel workers sequential kaam nahi bacha sakteBinary search (parent mein Example 2) mein 30 steps hote hain jahan har step ko pichle step ki comparison chahiye — dependencies ki ek chain. Isme 4000 GPU cores lagane se zero faayda hoga, kyunki 3999 cores bas wait karte rehenge. Isliye parent ka binary-search example CPU ko jeettne deta hai . Independence, core count nahi, woh cheez hai jo GPU ko chahiye.
Symbols ka aakhri cluster yeh hai ki GPU slow memory se bina bade caches ke kaise deal karta hai.
Definition Thread, warp, SM, occupancy
Ek thread ek running task hai — software worker jo ek instruction stream execute kar raha hai.
Ek warp 32 threads ka ek fixed bundle hai jise GPU hamesha saath chalata hai: saare 32 ek hi tick par same instruction run karte hain. Is scheme ko SIMT (Single Instruction, Multiple Threads) kehte hain.
Ek SM (Streaming Multiprocessor) GPU cores ka ek cluster hai jo ek saath kaafi saare warps hold karta hai.
Occupancy = GPU ke cores ka woh fraction (0 se 1) jo abhi actually compute kar rahe hain, stalled ya wait nahi kar rahe.
Intuition Latency hiding = spare runners ko warm-up mein rakhnaJab ek warp DRAM se data maangta hai, usse hundreds of cycles wait karna padta hai. Idle baithne ke bajaye, SM turant ek alag warp par switch kar leta hai jo run karne ke liye ready hai. Dozens of warps loaded rehne se hamesha koi na koi ready rehta hai, isliye lambi memory wait doosron ke kaam ke peeche chhupp jaati hai . Isliye GPU woh giant cache skip kar sakta hai jo CPU ko chahiye: woh storage (cache) ko spare workers (warps) se trade karta hai.
Definition Branch divergenceEk warp ke andar saare 32 threads ko same instruction run karna hota hai. Agar koi if kuch threads ko ek taraf aur baaki ko doosri taraf bheja, to GPU ko dono paths ek ke baad ek run karne padte hain , un threads ko off karte hue jo belong nahi karte — yeh serial slowdown branch divergence hai. Ek CPU iss dard se branch predictor se bachta hai; GPU ke paas yeh nahi hota, isliye divergence hurt karta hai.
data dependency vs independence
GPU vs CPU design philosophy
Vault mein yeh threads aage kahan jaate hain: memory ki kahaani 6.2.03-memory-hierarchy-GPU mein gehri hoti hai, warp/SIMT idea 6.3.01-SIMD-vs-SIMT mein, programming side 6.2.02-CUDA-programming-model aur 9.2.01-parallel-programming-models mein, speedup ki limits 9.1.02-Amdahls-law mein, aur is poore hardware ka ancestor 6.1.01-von-Neumann-architecture mein.
Daayaan side dhako; reveal karne se pehle apna jawaab zor se bolo.
Latency kya hai, ek sentence mein? Woh time jab ek single task shuru hota hai jab tak wahi task khatam hota hai.
Throughput kya hai, aur yeh latency se kaise alag hai? Time ki unit mein khatam hone wale tasks ki sankhya — ek rate, jabki latency ek single duration hai.
Kya ek machine mein ek saath high latency AUR high throughput ho sakti hai? Haan — conveyor belt: har item mein zyada time lagta hai (high latency) lekin har second ek item girta hai (high throughput).
T = P N × t t a s k P N P
IPC ka matlab kya hai? Instructions Per Cycle — chip ek clock tick mein kitne instructions khatam karta hai.
I P C × f c l oc k (instructions per tick) × (ticks per second) = instructions per second.
Transistor budget B Die par transistors ki fixed sankhya; cache/control par kharach karne se compute ke liye kam bachte hain.
Cache size ko transistors mein convert karo: recipe kya hai? megabytes × 8 (bits per byte) × 6 (transistors per SRAM bit).
Data dependency kya hoti hai? Jab ek task ko shuru hone se pehle doosre task ka result chahiye, jo sequential order force karta hai.
"Embarrassingly parallel" ka matlab kya hai? Tasks mein bilkul koi dependencies nahi, har ek isolation mein chalane layak.
Ek warp kitna bada hota hai, aur SIMT ka matlab kya hai? 32 threads; Single Instruction Multiple Threads — saare 32 ek saath same instruction run karte hain.
GPU bade caches ke bina memory latency kaise hide karta hai? Jab ek warp wait karta hai, doosre ready warp par switch kar leta hai, cores ko busy rakhta hai.
Branch divergence kya hai? Jab ek warp ke threads alag if paths lete hain, GPU ko har path serially run karna padta hai.
