5.4.17 · D4 · HinglishMemory Hierarchy & Caches

ExercisesPrefetching strategies

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5.4.17 · D4 · Hardware › Memory Hierarchy & Caches › Prefetching strategies

Figure — Prefetching strategies

Level 1 — Recognition

Recall Solution 1.1

Accuracy issued prefetches ke upar hai: . Coverage original misses ke upar hai: . Alag denominators — yahi pura point hai. Dono mein aate hain jaise hona chahiye. Accuracy ::: 0.30 Coverage ::: 0.48

Recall Solution 1.2

(a) Next-line — consecutive elements, ek line ke barabar stride; +1 rule ise pakad leta hai. (Stride bhi kaam karta hai, next-line sabse sasta option hai jo kaam kare.) (b) Stride — ek element se bada constant gap; next-line beech ke har element ko miss kar deta. (c) Correlation — agla address jo bhi pointer hold karta hai wahi hai; koi arithmetic pattern nahi, isliye sirf recorded miss-pairs (A→B) help karte hain. Spatial vs Temporal Locality se relate karta hai. (a) ::: next-line (b) ::: stride (c) ::: correlation


Level 2 — Application

Recall Solution 2.1

Har access pay karta hai; sirf miss fraction penalty pay karta hai. AMAT_base ::: 6.8 cycles

Recall Solution 2.2

Step 1 — effective miss rate. kyun subtract karte hain? Socho 100 misses 100 tickets ki tarah lined up hain. Coverage matlab prefetcher ne physically 65 tickets CPU ke paunchne se pehle phaad diye — wo 65 accesses ab cache mein hit karte hain. Sirf bache hue tickets () abhi bhi miss karte hain. Yeh literally upar ki figure ka green-slice-removed picture hai: miss bar se par aa jaata hai. Yahan koi accuracy factor nahi hai — coverage pehle se hi correctness aur timeliness fold kar leta hai (yeh fraction actually eliminate hue hai). Step 2 — naya AMAT. Same formula, choti miss fraction: Step 3 — speedup. . m_eff ::: 0.014 AMAT_pf ::: 3.68 cycles speedup ::: about 1.85x

Recall Solution 2.3

Confirmed stride (aur , — sab agree karte hain). Neeche ka address-line diagram exactly yahi trace karta hai: violet dots observed accesses hain, orange squares ke baad issue hone wale teen prefetches hain. Latest address se ke liye prefetch karo:

Sabse door wali aage ki distance bytes. prefetched ::: 2192, 2240, 2288 farthest distance ::: 144 bytes

Figure — Prefetching strategies

Level 3 — Analysis

Recall Solution 3.1

Figure ki two-slice picture use karo: remove hone wala green slice hai, lekin add hone wala magenta pollution slice hai — pollution benefit se zyada hai, isliye compute karne se pehle hi loss expect karo. Baseline: cycles. Yeh hurt karta hai cycles per access se. Kam accuracy ne coverage bhi shrink ki aur bekaar prefetches ne live lines evict kiye (dekho Cache Pollution and Replacement Policies). m_eff ::: 0.073 AMAT_pf ::: 8.3 cycles AMAT_base ::: 7.0 cycles net change ::: +1.3 cycles (worse)

Recall Solution 3.2

Break-even woh moment hai jab magenta slice exactly green slice ke barabar ho — miss bar wapas original height par aa jaata hai. Formally : se zyada koi bhi pollution net loss bana dega. Ex 3.1 mein — exactly isliye hurt kiya. Note karo hamesha, stated domain ke consistent hai. break-even pollution ::: 0.012

Recall Solution 3.3

Coverage "issued for" aur "succeeded" ka product hai: . aur dono mein hain, isliye unka product bhi — koi domain violation nahi. coverage ::: 0.45 m_eff ::: 0.0275 AMAT ::: 3.75 cycles


Level 4 — Synthesis

Recall Solution 4.1

Fully hide karne ke liye time cycles. Har line cycles of compute "consume" karti hai. Isliye prefetch itna lead karna chahiye: 15 lines se kam ahead chalna matlab prefetch late hai (partial miss). Bahut zyada aage chalna live data ko bahut jaldi evict karne ka risk rakhta hai. Yahi wajah hai ki degree/distance tuning matter karti hai — Memory-Level Parallelism (MLP) aur Out-of-Order Execution se connect karta hai. distance ahead ::: 15 lines

Recall Solution 4.2

Blocking se pehle, access pattern rows ke across jump karta tha — irregular, isliye hardware stride prefetcher koi stride lock nahi kar sakta tha, aur software hint (ya correlation prefetcher) chahiye tha. Blocking ke baad, inner loop contiguous elements walk karta hai = unit stride. Ek simple hardware next-line / stride prefetcher yeh automatically detect kar leta hai zero instruction cost mein. Isliye explicit PREFETCHT0 redundant ho jaata hai: yeh sirf instruction bandwidth spend karega ek aise pattern ke liye jise hardware pehle se hi cover karta hai. Key insight: locality improve karna (blocking) expensive software prefetching unnecessary bana sakta hai — prefetch instructions add karne se pehle data restructure karo. sufficient mechanism ::: hardware next-line / stride prefetch


Level 5 — Mastery

Recall Solution 5.1

AMAT ko ka function likho (yaad rakho ): ke saath: ka coefficient hai. Isliye badhne par decrease karta hai — yahan zyada coverage hamesha help karta hai kyunki pollution penalty (coverage per unit ) benefit se chhoti hai (coverage per unit ). Yeh figure ka rule hai: green slice per unit hataaya () magenta slice per unit add hue () se zyada hai. Isliye optimum sabse bada achievable hai, yaani (coverage ki domain ki top): Interpretation: jab bhi pollution-per-coverage ho, coverage ko ceiling tak push karo; agar yeh se zyada ho, coefficient positive flip ho jaata hai aur best choice hai (prefetcher band kar do). Break-even slope exactly hai. coefficient of c ::: -0.03 optimal coverage ::: 1 AMAT_min ::: 8.5 cycles

Recall Solution 5.2

Coverage (issued × success): . (Note: accuracy ek bandwidth metric hai — yeh coverage mein enter NAHI karta.) Pollution unused prefetches se: (positive, aur , isliye domain ke andar). Effective miss rate: . AMAT: cycles. Baseline: cycles. Net win cycles per access — kyunki green slice () hataaya gaya magenta pollution slice () add hue se zyada hai. coverage ::: 0.35 pollution ::: 0.008 m_eff ::: 0.0405 AMAT ::: 5.05 cycles net gain ::: 0.95 cycles


Recall Self-check summary

Formula for effective miss rate ::: m_eff = m(1-c) + delta_m Formula for AMAT ::: t_hit + m_eff * t_miss Coverage denominator ::: original misses Accuracy denominator ::: prefetches issued Break-even pollution ::: delta_m = m * c Coverage domain ::: 0 <= c <= 1 Pollution domain ::: delta_m >= 0 (typically <= m) Timely prefetch distance ::: ceil(t_miss / cycles_per_line) lines

Parent bhi dekho: Prefetching strategies aur Hinglish companion 5.4.17 Prefetching strategies (Hinglish).