MESI - MOESI coherence protocols

5.4.15 · Hardware › Memory Hierarchy & Caches

WHY coherence ko ek protocol ki zaroorat hai?

Socho do cores hain, dono ke paas private L1 cache hai, aur woh address X = 5 share kar rahe hain.

• Core 0 X load karta hai → X=5 cache karta hai.
• Core 1 X load karta hai → X=5 cache karta hai.
• Core 0 X=9 apni cache mein likhta hai (fast, memory trip nahi).
• Core 1 ab apni cache se X padhta hai → 5 milta hai. ❌ Stale!

Hardware ko Single-Writer / Multiple-Reader (SWMR) invariant guarantee karni hi padti hai:

Coherence protocols SWMR ko enforce karte hain — har cache line ka state track karke aur shared bus (ya directory) par snooping karke ki doosri caches kya kar rahi hain.

MESI states — HAR letter ka MATLAB

Har cache line 2 bits state carry karta hai:

WHY four states, do nahi? Naive "Valid/Invalid" scheme har write par bus broadcast force karta hai. E ek clever optimization hai: agar tum ek clean line ke sirf ek holder ho, toh E→M transition karke silently likh sakte ho (koi bus traffic nahi). Isliye kisi private variable ko load karke modify karna sasta hai.

HOW state transitions kaam karte hain (SWMR se derivation)

Hum transitions derive karte hain yeh puch ke: "SWMR ko sach rakhne ke liye kya hona chahiye?"

Local read (Core load karta hai):

• Agar line M/E/S hai → hit, same raho.
• Agar I hai → read miss. BusRd broadcast karo.
  • Agar koi doosri cache ke paas hai → woh supply karta hai (ya memory); tum S mein land karte ho. M mein koi bhi cache pehle write back karega.
  • Agar koi nahi rakhta → tum E mein land karte ho (tum sole owner ho). WHY E? Kyunki ab tum jaante ho ki tum exclusive ho, baad mein silent write enable ho jaata hai.

Local write (Core store karta hai):

• Agar M hai → hit, M hi raho.
• Agar E hai → silently E→M jao (koi bus traffic nahi!). WHY allowed? Tum akele holder ho, toh kisi aur ko invalidate karne ki zaroorat nahi.
• Agar S hai → BusRdX (Read-for-Ownership) broadcast karo taaki baaki saari copies invalidate ho jayein, phir S→M jao. WHY? SWMR: likhne se pehle tum single writer hone chahiye.
• Agar I hai → write miss: BusRdX broadcast karo, data fetch karo, doosron ko invalidate karo, M mein land karo.

Snooped (remote) events — bus par react karo:

• M mein ho aur BusRd dekho → koi padhna chahta hai; supply/flush karna padega → M→S jao (aur memory update karo).
• E mein ho aur BusRd dekho → E→S jao (ab shared).
• BusRdX (ya invalidate) kisi bhi valid state mein suno → → I jao. Agar M mein the, toh pehle write back karo (akeli sahi copy mat kho!).

MOESI — O (Owned) state add karna

WHY O add karein? Plain MESI mein, jab M mein koi core BusRd sunta hai, toh use M→S transition karna padta hai aur dirty data memory mein write back karna padta hai. Woh write-back expensive hai aur aksar waste hota hai (value jald hi phir badal sakti hai).

MOESI ke saath:

• BusRd par, M holder M→O jata hai instead of M→S. Woh dirty data apne paas rakhta hai, owner ban jaata hai, aur data directly requester ko forward karta hai (cache-to-cache transfer). Memory update NAHI hoti. Requesters ko S milta hai.
• Sirf jab owner finally evict hota hai tab memory likhi jaati hai.

MOESI states: M, O, E, S, I (5 states, 3 bits).

Worked examples

Common mistakes (steel-manned)

Active recall

Flashcards

Connections

• Cache Coherence vs Memory Consistency — coherence = per-location ordering; consistency = across-location ordering.
• Snooping vs Directory-based protocols — messages actually kaise deliver/scale hote hain.
• Write-back vs Write-through caches — M state sirf write-back ke saath sense karta hai.
• False Sharing — ek line par unrelated data ki wajah se coherence traffic.
• MOESI in AMD aur MESIF in Intel — real-world variants (F = Forwarder).
• Memory Hierarchy & Caches — parent chapter.
• Bus arbitration & interconnect — woh medium jo BusRd/BusRdX carry karta hai.

Concept Map