5.4.12
Intuition Ek sentence mein ideaVirtual memory ko har memory access par page table lookup chahiye hoti hai — virtual address ko physical mein convert karne ke liye — lekin woh lookup khud memory mein rehti hai, toh har access double (ya aur zyada) slow ho jaata. TLB ek tiny, fast cache hai jo recent virtual→physical page translations yaad rakhti hai , taaki CPU almost hamesha slow page-table walk skip kar sake.
Intuition Woh problem jo yeh solve karta haiPaging ke under, CPU virtual addresses (VA) produce karta hai. Memory touch karne se pehle, hardware ko page table padh ke physical address (PA) dhundhna padta hai — jo khud DRAM mein hai.
Bina help ke: 1 program memory access = 1 page-table read + 1 data read = kam se kam 2× slower .
Multi-level page tables ke saath (jaise x86-64 par 4 levels): ek walk = 4 DRAM reads → up to 5× slower !
Locality humein bachati hai: programs baar baar same thode se pages touch karte hain. Toh translations ko cache karo. Wahi cache TLB hai.
Ek Translation Lookaside Buffer ek small, fast (aksar fully- ya set-associative) hardware cache hai jo recently-used virtual-page-number → physical-frame-number mappings store karta hai, saath mein permission/status bits ke. Yeh MMU ke andar baitha hai aur har memory reference par consult kiya jaata hai.
Ek address page part aur offset mein split hota hai:
VA = virtual page number VPN ∥ within page offset
Offset translate nahi hota — sirf page number hota hai. Toh TLB VPN → PFN (physical frame number) map karta hai, aur:
PA = ( PFN ≪ log 2 P ) ∥ offset
jahan P
Har memory access par:
VA ko VPN + offset mein split karo.
TLB mein VPN lookup karo.
TLB hit → PFN turant milo → PA banao → cache/memory access karo.TLB miss → poora page-table walk karo (hardware ya OS) PFN lene ke liye → TLB mein insert karo → retry karo.
Valid aur permission bits bhi check karo (read/write/execute, user/kernel). Violation fault raise karta hai.
Worked example Ek concrete TLB hitSystem: P = 4 VPN 0x00012 → PFN 0x0037 hold kar raha hai.
Access VA = 0x00012ABC .
Step: split karo → offset = low 12 bits = 0xABC; VPN = high 20 bits = 0x00012. Kyun? 4 2 12 Step: 0x00012 ke liye TLB lookup → hit , PFN = 0x0037.Step: PA = (PFN << 12) | offset = 0x0037 left shift 12 = 0x00037000, OR 0xABC = 0x00037ABC . 12 se shift kyun? Kyunki PFN ek 4KiB frame ko name karta hai; frame size se multiply karne par (<< 12 Result: koi page-table walk nahi chahiye.
Intuition Hum ise quantify kyun karte hainHum prove karna chahte hain ki TLB actually help karta hai, aur kitna, toh hum EMAT first principles se derive karte hain.
Maano:
h t TLB t m ek walk mein W L L
Hit par: TLB search + ek data access = t TLB + t m Miss par: TLB search + walk (W ⋅ t m t TLB + W t m + t m
Probability se weight karke:
EMAT = t TLB + t m + ( 1 − h ) W t m
Worked example Numbers plug karot TLB = 1 t m = 100 W = 1 h = 0.98
Step: extra miss cost = ( 1 − 0.98 ) ( 1 ) ( 100 ) = 2 Kyun? sirf 2% accesses walk karte hain, har ek t m Step: EMAT = 1 + 100 + 2 = 103 100 ke itna close kyun? High hit rate walk ko almost invisible bana deta hai.Compare h = 0.90 = 0.10 × 100 = 10 = 111 10% miss overhead triple karta hai — hit rate bahut matter karta hai.
stale ya wrong-process data hold kar sakta hai
TLB ek specific address space ke liye mappings hold karta hai. Context switch par, process A ka VPN 0x5 ≠ process B ka VPN 0x5. Do fixes hain:
Switch par TLB Flush karo (simple, lekin cold TLB → baad mein miss storm).
ASID/PCID (Address-Space IDs): har entry ko process id se tag karo taaki entries coexist karein; flush ki zaroorat nahi.
Agar OS page table entry change kare (ek page unmap kare), toh stale TLB entry invalidate karni padegi — ek TLB shootdown (multicore par, ek IPI doosre cores ko bhi invalidate karne kehta hai).
Common mistake "Offset bhi translate hota hai."Kyun sahi lagta hai: translation poora address convert karta lagta hai, toh log sab bits transform karte hain.
Fix: VA aur PA ka offset same hota hai — sirf page/frame number change hota hai. Bytes apni position page ke andar rakhte hain; paging sirf poore page ko ek alag frame mein move karta hai. Toh low log 2 P
Common mistake "TLB miss ka matlab page fault hai."Kyun sahi lagta hai: dono translation ke dauran "misses" hain.
Fix: TLB miss = translation cached nahi hai, lekin page memory mein hai → bas page table walk karo (fast, no disk). Page fault = page physical memory mein hai hi nahi → OS ko disk se load karna padega (thousands× slower). TLB miss ≠ page fault.
Common mistake "Bada TLB hamesha jeet ta hai."Kyun sahi lagta hai: zyada entries = higher hit rate.
Fix: Bada/associative TLB slower hota hai aur power/area kharach karta hai, aur yeh har access ke critical path par hota hai. Real designs multi-level TLBs use karte hain (small fast L1 TLB + bigger L2 TLB) — same idea jaise data caches mein.
Recall Woh 20% jo 80% deta hai
TLB VPN→PFN cache karta hai; offset untranslated rehta hai.
Flow: hit → done; miss → page-table walk , phir fill.
EMAT = t TLB + t m + ( 1 − h ) W t m TLB miss ≠ page fault.
Context switch → flush ya ASID tags.
Recall Feynman: 12-year-old ko samjhaoSocho tumhare school mein hazaaron lockers hain, lekin woh map jo batata hai tumhara locker kaunsa hai woh principal ke office mein door rakha hai. Har baar book lene ke liye tumhe office jaana padta, map padhna padta, phir locker tak jaana padta — bahut slow. Toh tum apni pocket mein ek sticky note rakh lo jisme tumhare sabse zyada use hone wale locker numbers hain. TLB wahi sticky note hai: pehle pocket check karo (fast!), aur sirf tab office (page table) tak jao jab note mein nahi hai.
"TLB = Translation Last-used Buffer." Yeh tumhari last-used page translations yaad rakhta hai. Aur flow ke liye: "Hit? Home. Miss? Map." (Miss → page table map padho jaake.)
TLB kya cache karta hai? Recently-used virtual-page-number → physical-frame-number translations (plus permission/valid bits).
Page offset kabhi translate kyun nahi hota? Paging poore pages ko frames mein move karta hai; ek byte apni position page ke andar rakhta hai, toh low log 2 P
4KiB page ke liye kitne offset bits? 12, kyunki 4 KiB = 2 12
TLB miss par kya hota hai? Page-table walk PFN dhundh ta hai, mapping TLB mein insert hoti hai, aur access retry hota hai.
TLB miss aur page fault mein kya farq hai? TLB miss = translation cached nahi lekin page memory mein hai (fast walk); page fault = page physical memory mein nahi (disk se load karna padega).
EMAT formula do. EMAT = t TLB + t m + ( 1 − h ) W t m h W
Hit rate itna zyada kyun matter karta hai? Extra cost ( 1 − h ) W t m h
Context switch par TLB handle karne ke do tarike? Poora TLB flush karo, ya entries ko ASID/PCID se tag karo taaki multiple address spaces coexist karein.
TLB shootdown kya hai? OS page change/unmap kare tab cores mein stale TLB entry invalidate karna (inter-processor interrupt ke zariye).
PFN aur offset se PA kaise banta hai? P A = ( PFN ≪ log 2 P ) ∣ offset
TLB ko huge kyun nahi banate? Yeh har access ke critical path par hai; bada = slower/zyada power. Isliye multi-level TLBs (L1 small+fast, L2 bigger).
Virtual Memory — TLB us address translation ko accelerate karta hai jo paging require karta hai.Page Table — woh slow structure jise TLB cache karta hai; miss par consult hota hai (the "walk").Cache (memory hierarchy) — same locality principle; VIPT caches TLB lookup ko cache indexing ke saath overlap bhi karte hain.Context Switch — TLB flush ya ASID handling trigger karta hai.Page Fault — ek alag miss: page RAM se absent hai, sirf TLB se nahi.Locality of Reference — isliye TLB ki small size bhi high hit rates deti hai.
Valid and permission bits
