Exercises — Branch target buffer (BTB)
This page tests everything from Branch target buffer (BTB). Work each problem before opening the solution. Levels rise from recognising what a BTB does to designing one. Every symbol used here is defined the moment it appears — no assumed background beyond the parent note.
Before we start, three quantities recur, so let's pin them down in plain words:
Level 1 — Recognition
Exercise 1.1
Which of these does the BTB store? (a) whether a branch is taken, (b) the address to jump to if taken, (c) the result of the compare, (d) the decoded opcode.
Recall Solution
Answer: (b) — the target address, the "where to jump".
- (a) is the branch predictor's job (direction).
- (c) is computed in the execute stage.
- (d) requires decode, which is exactly the step the BTB lets us skip. The BTB answers only: "If taken, where?"
Exercise 1.2
At what pipeline stage does the BTB lookup happen, and what does it run in parallel with?
Recall Solution
The lookup happens in the fetch stage, using the current program counter (PC — the address of the instruction we are fetching now). It runs in parallel with the Instruction Cache (I-Cache) access. Both are indexed by the same PC at the same time, so the target arrives before decode — no waiting.
Exercise 1.3
A BTB has 256 entries. How many index bits are needed, and why do we usually skip the lowest 2 bits of the PC when forming that index (assume 4-byte instructions)?
Recall Solution
- , so we need 8 index bits.
- Instructions are 4 bytes = , so PC bits are always for aligned instructions — they carry no information to distinguish branches. We skip them and use bits .
Level 2 — Application
Exercise 2.1
A pipeline loses 2 cycles on every mispredicted-or-missed taken branch. Branches are 20% of instructions; 60% of branches are taken. Without any BTB, every taken branch pays the full 2-cycle penalty. Compute the average cycles lost per instruction.
Recall Solution
Fraction of instructions that are taken branches: Each pays 2 cycles:
Exercise 2.2
Now add a BTB with hit rate and predictor accuracy . A taken branch escapes penalty only if it hits AND is predicted right. Penalty stays 2 cycles. Same branch/taken fractions as 2.1. Find cycles lost per instruction.
Recall Solution
Probability a taken branch escapes = . Probability it pays = . Taken-branch fraction of all instructions = (from 2.1).
Exercise 2.3
Using 2.1 and 2.2, what fraction of the original branch penalty did the BTB+predictor remove?
Recall Solution
Notice this equals exactly — the escape probability. That's not a coincidence: the only thing that changed is that each taken branch now escapes with probability .
Level 3 — Analysis
Exercise 3.1 (Aliasing)
A BTB has 64 entries, indexed by PC bits . Two branches sit at 0x1080 and 0x1880. Show their index, and explain what happens to performance when they execute alternately in a loop.
Recall Solution
Index = PC = bits 7 down to 2.
0x1080=...0001 0000 1000 0000. Bits =100000= 0x20.0x1880=...0001 1000 1000 0000. Bits =100000= 0x20. Same index → they share one BTB slot. Alternating execution:
0x1080writes tag0x1080into slot 0x20.0x1880overwrites it with tag0x1880.- Back to
0x1080: index hits slot 0x20, but tag0x1880≠0x1080→ miss, full penalty. Then it overwrites again. Every iteration both branches miss: 100% miss rate despite each being perfectly predictable. Correctness is preserved (the tag check refuses the wrong target), but speed collapses. See figure below.

Exercise 3.2
For 3.1, propose the smallest change to the BTB organisation (not size) that eliminates the thrashing, and state the new outcome.
Recall Solution
Make the BTB 2-way set-associative: each index now holds 2 entries (see Cache Organization). Both 0x1080 and 0x1880 map to set 0x20 but live in different ways, so neither evicts the other. Result: after warm-up both hit every iteration — thrashing gone, no size increase needed (though total entries double for the same number of sets).
Exercise 3.3
A loop runs a taken branch 1000 times. The first execution is a cold miss costing 3 cycles; the other 999 hit and cost 0. What is the average penalty per execution, and why does the cold miss barely matter?
Recall Solution
The cold miss is a one-time cost amortised over many hits. This is why BTBs shine in loops: the expensive learning happens once, then thousands of free reuses follow.
Level 4 — Synthesis
Exercise 4.1 (BTB + RAS)
A function is called from many sites and returns via ret. A ret is an indirect branch: its target changes every call. Explain why a plain BTB predicts ret targets poorly, and which structure fixes it.
Recall Solution
A plain BTB stores one target per branch PC. But a single ret instruction jumps back to whichever caller invoked the function — a different address each time. The BTB keeps only the last return address, so the next return from a different caller mispredicts.
Fix: the Return Address Stack (RAS) — a small hardware stack. Each call pushes its return address; each ret pops it. Because calls/returns nest like matched parentheses, the RAS gives the correct target even when it changes every time — something a single-target BTB entry cannot.
Exercise 4.2 (Design trade-off)
You may spend a fixed transistor budget on either a bigger BTB (fewer capacity misses) or a better predictor (higher accuracy ). Given the escape probability , argue which to prioritise if currently but .
Recall Solution
Escape probability . Marginal gain from improving each factor:
- Improving from 0.99: at most possible → escape rises by .
- Improving from 0.80: room up to → escape rises by up to . is the bottleneck — it's far from 1 while is nearly saturated. Spend on the predictor. General rule: invest in whichever factor is furthest below 1, because is limited by its weaker term.
Exercise 4.3 (Interaction with delay slots)
An old ISA uses a branch delay slot (the instruction after a branch always executes). Does a BTB still help such a machine? Explain.
Recall Solution
The delay slot hides one cycle of branch latency by always running the next sequential instruction — useful work regardless of direction. But if the branch target needs more than one cycle to become known (deep pipeline, decode + target calc = 2 cycles), a single delay slot cannot cover it. A BTB supplies the target in the fetch cycle, covering the remaining gap. So yes — the BTB still helps by removing the remaining penalty the fixed-size delay slot can't hide.
Level 5 — Mastery
Exercise 5.1 (End-to-end model)
A machine: branches = 25% of instructions; 70% of branches taken; taken-branch penalty cycles; BTB hit rate ; predictor accuracy . Base CPI (cycles per instruction assuming no branch penalty) = 1.0. Compute (a) taken-branch fraction of all instructions, (b) probability a taken branch pays, (c) added CPI from branch penalties, (d) final CPI.
Recall Solution
(a) Taken-branch fraction . (b) Escape ; pay . (c) Added CPI . (d) Final CPI .
Exercise 5.2 (Break-even)
Take the machine of 5.1 but let predictor accuracy be a variable. What accuracy makes the added branch CPI drop to ? (Keep , , taken fraction .)
Recall Solution
Added CPI . Since is impossible, this target is unreachable with alone. To hit 0.05 you must also raise (or lower ). This is the mastery lesson: the product caps how low the penalty can go, and no single knob past its ceiling of 1 can rescue an over-ambitious target.
Exercise 5.3 (Full comparison)
Compare added branch CPI for the 5.1 machine (a) with no BTB (every taken branch pays ) versus (b) the BTB machine of 5.1. State the speedup in branch-penalty CPI removed.
Recall Solution
(a) No BTB: added CPI . (b) With BTB (from 5.1c): added CPI . Penalty CPI removed . Fraction removed — again exactly , the escape probability. The whole benefit of the BTB collapses to that one product.
See Also
- Parent: Branch target buffer (BTB)
- Pipeline Hazards · Speculative Execution · Return Address Stack (RAS) · Cache Organization · Instruction Cache (I-Cache) · Branch Delay Slots