Question bank — 2-bit saturating counter predictors

False. TNTNTN... jaisi alternating pattern ke liye dono predictors ~50% par baithe rehte hain kyunki koi bhi period-2 behaviour track nahi kar sakta; 2-bit sirf biased ya loopy branches par jeetta hai.

False. Saturating ka matlab hai clipping: 11 + 1 = 11 (rukta hai), kabhi 00 nahi. Wrapping usi hysteresis ko destroy kar deta jo is design ka reason hai.

True guess ke liye (T vs NT), lekin low bit "strength" hai jo hysteresis store karta hai — ye decide karta hai ki ek galat outcome prediction flip karega ya sirf use weaken karega.

False. Real branches ~60–70% taken hoti hain, isliye 00 most cold starts ko mispredict karta hai; commercial designs 10 (Weakly Taken) par init karte hain taaki common case ki taraf warm-start ho sake.

True. Loop exit par counter sirf 11→10 drop karta hai (phir bhi TAKEN predict karta hai), isliye agli loop entry correctly predict hoti hai — re-entry miss gayab ho jaati hai.

False. Returns sharply diminish hote hain; 2-bit ~95% benefit capture karta hai. Extra bits hysteresis add karte hain jo phase changes par adaptation delay karta hai aur storage per entry double kar deta hai.

False. Steady-state cost ek miss per loop instance hai (unavoidable exit), har iteration par nahi — body iterations sab correct hote hain jab counter 11 par saturate ho jaata hai.

False aligned instructions ke liye. Wo bits hamesha 00 hote hain (4-byte alignment), isliye koi discriminating information nahi lete; unhe rakhna table space waste karta.

Ek not-taken 11→10 (WT) move karta hai, jiska MSB phir bhi 1 hai, isliye wo abhi bhi taken predict karta hai. Guess flip karne ke liye tumhe 01 reach karne ke liye do consecutive not-takens chahiye.

Har entry 2 bits hai, 8 nahi. Cost hai $4096\times 2=8\text{Kbit}=1\text{KB}$, claim se chaar guna chhoti.

NT-biased aur T-biased branch ke beech ek bhi collision destructive interference cause karta hai: shared counter thrash karta hai aur dono mispredict karte hain. Badi tables collision ki probability kam karti hain, effect nahi.

Updates actual outcome par depend karte hain, correctness par nahi: taken → increment, not-taken → decrement, chahe kuch bhi predict kiya ho.

1-bit predictor steady-state mein do baar per instance mispredict karta hai (exit use NT par flip karta hai, re-entry use T par wapas flip karta hai). 2-bit sirf single unavoidable exit miss leta hai.

Wo 1-bit predictor mein collapse ho jaata hai. Weak states hi hysteresis buffer hain; unhe hatana har anomaly par ping-ponging wapas la deta hai.

Power of two ka modulo sirf ek bit-slice hai (bitwise AND with $2^k-1$) — koi divider nahi, ek wire cut, hardware mein essentially free.

Ek anomaly counter ko same half ke andar ek step nudge karta hai (jaise 11→10), isliye MSB aur thus prediction survive karta hai; ek genuine, repeated change eventually use 10/01 boundary ke across push kar deta hai.

Wo extreme cells 00/11 hain; ek confirming outcome jo tumhe wahin rakhta hai kuch cost nahi karta, aur ek single contrary outcome sirf ek "unit" stored momentum spend karta hai bina guess change kiye.

Ye common case par bet karta hai (branches taken lean karti hain) ek step flip se door rehte hue, isliye ek genuinely not-taken branch jaldi correct ho jaati hai — warm-start benefit aur over-commitment ke beech balance karta hai.

Counter ek majority direction track karta hai, lekin TNTN ka kisi bhi short window mein koi majority nahi hoti; har outcome pichle update ko cancel karta hai, isliye ye middle ke around oscillate karta hai aur har baar galat predict karta hai.

Phase change ka matlab hai branch ka true behaviour genuinely reverse ho gaya hai; deep counters ko middle cross karne ke liye bahut zyada outcomes chahiye (jaise 3-bit ke liye 4), isliye ye transition ke dauran mispredicting karte rehte hain — hysteresis stubbornness ban jaati hai.

Bimodal prediction assume karta hai ki har branch ka apna bias hai apne address par captured; history ke saath correlating ek alag, zyada powerful scheme hai — dekho Two-Level Adaptive Predictors aur Gshare Predictor.

Ye sirf direction predict karta hai (T/NT); target address ek alag BTB (Branch Target Buffer) se aata hai. Direction + target milkar pipeline ko Pipeline Hazards se bachne dete hain.

Counter 11 tak climb karta hai aur wahin rehta hai (saturation) — koi overflow nahi, koi wrap nahi, prediction strongly taken rehti hai.

Pure cold-start hai: outcome sirf ek miss ya hit hai jo sirf initialization aur actual direction par depend karta hai; hysteresis kabhi engage nahi hoti kyunki doosri occurrence hi nahi hai.

Haan. Counter apne current 2 bits se aage memoryless hai — 10 tak kaise pohunche uski history gayi; dono taken predict karte hain aur dono future outcomes par identically respond karte hain.

Bahut achha. Long runs counter ko saturate karne dete hain aur ye sirf har run ki do boundaries par mispredict karta hai, TNTN ke unlike jahaan har step ek boundary hai.

Do. Ek saturated state (11 ya 00) se MSB boundary cross karne aur guess flip karne ke liye do contrary outcomes lagte hain — isliye prediction adapt hone se pehle maximum do straight misses.

Ye kabhi settle nahi karta — taken branch ise upar drive karti hai aur not-taken branch neeche, middle ke around oscillate karta hai aur dono ko aksar mispredict karta hai: classic destructive aliasing.