Foundations — Reorder buffer (ROB)

5.3.5 · D1 · Hardware › Advanced Microarchitecture › Reorder buffer (ROB)

Is page mein koi assumption nahi hai. Reorder buffer (ROB) padhne se pehle tumhare paas kuch words aur pictures honi chahiye. Hum har ek ko ground up se build karte hain, ek aisi order mein jahan har symbol use hone se pehle earn kiya ja chuka ho.

0. "Instruction" kya hota hai?

Hum instructions aise likhenge:

$\text{ADD }{R}_1,R_2,R_3$

Isko padhein: "box $R_2$ ki value lo, box $R_3$ ki value se add karo, sum ko box $R_1$ mein rakho." Boxes $R_1,R_2,R_3$ ko registers kehte hain — unhe hum aage define karte hain.

1. Registers aur register file

Figure dekho: register file sirf labelled cups ki ek row hai. $\text{RF}[R_1]$ cup $R_1$ ke andar ki value ko point karta hai. Jab ek program ek instruction ko sach mein "finish" karta hai, toh answer in cups mein se ek mein daal diya jaata hai — aur ek baar daal diya, toh woh permanent aur program ko visible ho jaata hai.

Register file ke contents ko hum architectural state kehte hain: woh state jo program ko honi chahiye. Related reading: Register-file-management.

2. Program order vs. execution order

Figure mein, left column program order hai (I1, I2, I3, I4 upar se neeche). Right column mein hai jab har instruction finish hoti hai: dekho I3 pehle finish hoti hai kyunki woh fast hai, chahe woh teesre number par likhi gayi thi. Yahi mismatch ROB ke existence ki poori wajah hai — dekhein Speculative-execution aur Superscalar-processors yeh samajhne ke liye ki processors out of order finish karne ki taklif kyun uthate hain.

3. In-flight instructions

4. Ek instruction ki teen life stages

Har instruction teen named moments se guzarti hai. Teeno tumhein verbatim pata honi chahiye.

Yeh trio Instruction-retirement mein puri tarah aata hai aur parent note ki backbone hai.

5. Queue, FIFO, aur "circular"

ROB ek FIFO hai kyunki retirement program order mein honi chahiye — pehle issue, pehle retire.

Figure mein $N=8$ slots ek ring ki tarah dikhaye gaye hain. Is ring par do arrows rehte hain:

Jaise instructions retire hoti hain, Head aage badhta hai. Jaise naye issue hote hain, Tail aage badhta hai. Dono ring ke around loop karte hain.

6. Ek hi math piece: modulo

Parent note mein mathematics se sirf ek hi symbol use hota hai — mod. Hum ise zero se define karte hain.

$\text{next\_tail}=(\text{tail}+1)\mathrm{mod}N$

7. Full vs. empty

Do conditions decide karti hain ki ring kaam accept ya release kar sakti hai ya nahi.

8. Ek slot ki status

Ek completed instruction jo head par nahi hai use wait karna padega — uska answer ROB slot mein baitha hai, register file mein nahi. Yeh waiting hi in-order retirement ka essence hai.

9. Tag / physical register name

10. Prerequisite map

Har arrow ka matlab hai "target samajhne se pehle source samajhna zaroori hai." Poora graph Reorder buffer (ROB) node mein funnel hota hai. Downstream topics jo in foundations ko reuse karte hain inmein Precise-exceptions, Branch-prediction, Memory-ordering, aur Instruction-retirement shamil hain.

Equipment checklist

Self-test: kya tum reveal karne se pehle har ek ka jawab de sakte ho?