Pipeline throughput and CPI: Question bank — Hinglish deep dive

5.2.9 · D5 · Hardware › Processor Datapath & Pipelining › Pipeline throughput and CPI

Yeh ek conceptual companion hai Pipeline throughput and CPI ke liye. Yahan koi number-crunching nahi hai — har item ek aisi soch ka tarika target karta hai jo logon ko ulajhata hai. Reveal cover karo, answer zor se bolo, phir check karo. Agar koi answer surprise kare, toh woh misconception tumhare dimag mein zinda thi.

Shuru karne se pehle, teen words ka exactly ek hi matlab hona chahiye, kyunki neeche ke zyaadatar traps actually inhi ke beech confusion hain:

performance-metrics identity ko poore waqt dhyan mein rakho: $Time = Instructions \times CPI \times T_{cycle}$ Har trap basically yahi sawaal hai: "in teen terms mein se actually change kis mein aaya?"

True or false — justify karo

Pipelining ek single instruction ki latency reduce karta hai.

False. Ek single instruction abhi bhi saare

k

stages traverse karti hai, isliye uski latency unchanged rehti hai (aksar

t_{r e g}

Ek 5-stage pipeline hamesha non-pipelined version se 5× faster chalti hai.

False. Speedup

\approx k

tabhi hota hai jab stages perfectly balanced hon aur

t_{r e g}

negligible ho. Stage imbalance aur register delay typically real 5-stage speedup ko 3–4× par cap kar dete hain.

Agar aap aur pipeline stages add karte raho, toh throughput indefinitely badhta rahega.

False. Har naya stage ek register add karta hai jiska

t_{r e g}

overhead shrinking clock period ka ek bada fraction ban jaata hai. ~10–15 stages ke baad, overhead aur extra hazard penalties diminishing (phir negative) returns cause karte hain.

CPI kabhi 1 se kam nahi ho sakta.

False. Ek scalar pipeline mein floor 1 hai, lekin ek superscalar processor har cycle mein kai instructions issue karta hai, isliye CPI 1 se kaafi neeche ja sakta hai (jaise 0.25 = 4 instructions/cycle).

Ideal pipeline CPI of 1 yeh assume karta hai ki instructions ki count infinite hai.

True (limit mein).

n

instructions ke liye exact CPI hai

\frac{k + n - 1}{n}

; yeh "

- 1

plus

k

" fill cost hai. Yeh sirf tab equal 1 hota hai jab

n \to \infty

; chhote

n

ke liye fill penalty significant hoti hai.

Faster clock ka matlab hamesha faster processor hota hai.

False. Performance = clock rate ÷ CPI. 5 GHz chip with CPI 4, 3 GHz chip with CPI 1 se slower hai. CPI ke bina clock speed meaningless hai.

Forwarding saare data hazards eliminate karta hai.

False. Forwarding unhi hazards ko remove karta hai jinका result already computed ho chuka hota hai jab zaroorat ho (EX→EX). Load-use hazard abhi bhi ek cycle stall karta hai kyunki loaded value MEM ke baad tak ready nahi hoti. Dekho 5.2.07-Forwarding-and-bypassing.

Ek stage ki delay ko aadha karke usse split karna hamesha throughput improve karta hai.

Zyaadatar true, ek catch ke saath. Yeh tabhi help karta hai jab woh stage bottleneck ho (yaani max wali). Non-critical stage split karna kuch nahi badalta siwaaye ek aur register ke overhead ke — pure loss.

Branch mispredictions CPI badhate hain chahe branches rare hon.

True but scaled. Penalty term hai Branch-rate × Mispredict-rate × Penalty; agar branches rare hain, toh poora product chhota hai, isliye CPI hit bhi chhota hoga — lekin zero kabhi nahi jab tak prediction perfect na ho.

Pipeline ka clock period saare stage delays ka sum hota hai.

False. Woh single-cycle period hota hai. Pipeline period hai

max (t_{i}) + t_{r e g}

— sirf sabse slow stage plus register overhead, kyunki stages concurrently chalte hain.

Galti dhundho

"5-stage design ko pipeline karne se meri ek instruction ki execution time ek-paanchwa ho jaati hai."

Galti yeh hai ki latency aur throughput ko confuse kiya ja raha hai. Teri ek instruction ko abhi bhi saare 5 stages chahiye; sirf instructions ki ek stream ke liye completions ki rate improve hoti hai.

"CPI = 1/k for a k-stage pipeline, isliye 5-stage pipeline ka CPI = 0.2 hai."

Galat.

k

stages ki count hai jo ek instruction pass karta hai (latency, cycles mein), yeh CPI ka divisor nahi hai. Ideal pipeline CPI 1 hai (har cycle mein ek completion),

1/ k

nahi.

"Stage delays ke sum mein register overhead

t_{r e g}

add karne se pipeline clock period milta hai."

Do galtiyan hain: sum ki jagah

max

use karo, aur

t_{r e g}

sirf ek baar us max mein add hota hai, sum mein nahi.

T_{p i p e} = max (t_{i}) + t_{r e g}

"CPI = 1.375 ke saath, hum ideal ke muqable mein 37.5% throughput kho dete hain."

Bilkul sahi nahi — throughput scale hota hai

1/ CPI

ke hisaab se, isliye actual throughput hai

1/1.375 = 72.7%

of ideal, yaani 27% loss, 37.5% nahi. CPI mein increase aur throughput mein loss alag-alag numbers hain.

"Structural hazards asli wajah hain kyun real pipelines CPI = 1 miss karti hain."

Overstated. Modern designs mein data hazards aur control hazards dominate karte hain; structural hazards ko duplicated resources aur split caches se largely design out kar diya jaata hai.

"Kyunki forwarding EX→EX bypass deta hai, load-use dependencies mein zero cycles lagte hain."

Load ka result sirf MEM stage ke baad appear hota hai, dependent ke EX ke liye ek cycle der se. Isliye load-use abhi bhi ek-cycle stall karta hai chahe full forwarding ho.

"Pipelining se speedup exactly stages ka ratio hota hai, isliye 14 stages ⇒ 14× speedup."

t_{r e g}

aur stage imbalance ko ignore kar raha hai. Real speedup

= \frac{\sum t _{i}}{m a x t _{i} + t _{r e g}}

hai, jo

k

se kaafi neeche hota hai jab overhead aur imperfect balance count ho.

Why questions

Hum clock period ke liye stage delays ka max kyun lete hain, average kyun nahi?

Saare stages usi clock edge par latch karte hain, isliye clock ko sabse slow stage finish hone ka wait karna padta hai. Average fast stages ko slow walo ki "help" karne deta — lekin physically woh kar nahi sakte; har stage ka apna fixed kaam hota hai.

Ek bubble (NOP) throughput kyun reduce karta hai lekin aas-paas ki instructions ki latency nahi badlaata?

Bubble ek wasted cycle hai jahan kuch retire nahi hota, completion rate kam ho jaati hai. Har real instruction abhi bhi apne

k

stages leta hai; bubble sirf completions ke beech idle time insert karta hai.

5-stage pipeline ka real speedup sirf 3–4× kyun hota hai 5× ki jagah?

Stages rarely equal hote hain, isliye clock sabse slow wale se set hoti hai (fast stages mein slack waste ho jaata hai), aur har stage boundary

t_{r e g}

overhead add karta hai. Dono theoretical

k

× factor ko erode karte hain.

Branch prediction accuracy improve karna throughput kyun help karta hai jabki clock nahi badlaata?

Better prediction misprediction stall term ko kam karta hai, jo CPI kam karta hai. Kyunki Time = Instr × CPI ×

T_{cy c l e}

, CPI kam karna same clock speed par execution time kam karta hai.

Pipeline stages add karna eventually performance kyun hurt karta hai?

Har stage fixed

t_{r e g}

wala ek register add karta hai, isliye jaise clock period shrink hoti hai, overhead ek bada fraction ban jaata hai. Deeper pipelines branch penalties (cycles mein) bhi bade kar dete hain, CPI badhaa dete hain.

CPI raw clock frequency se better performance predictor kyun hai?

Frequency sirf cycle rate batati hai; CPI batata hai ki har instruction actually kitne cycles cost karti hai. Sirf unka combination (rate ÷ CPI) real kaam per second ko reflect karta hai.

Ek superscalar processor CPI 1 se neeche report kar sakta hai jabki scalar pipeline nahi kar sakta, kyun?

Ek scalar pipeline har cycle mein zyada se zyada ek instruction retire karta hai (floor CPI = 1). Ek superscalar core mein multiple execution units hote hain aur woh har cycle mein kai retire karta hai, isliye cycles ÷ instructions 1 se neeche aa jaata hai.

Edge cases

Exactly ek instruction execute karne wali pipeline ka CPI kya hai?

Yeh

k

hai (fill cost), kyunki woh akeli instruction bina kisi overlap ke saare

k

stages traverse karti hai jisko amortize kiya ja sake. "CPI ≈ 1" ka claim sirf lambi instruction streams ke liye sach hai.

Agar instruction stream pipeline depth se chhoti ho (

n < k

), throughput ka kya hoga?

Pipeline drain hone se pehle kabhi fully fill nahi hoti, isliye overlap minimal hai aur effective CPI non-pipelined case ke paas pahunch jaata hai — chhote bursts ke liye pipelining almost koi benefit nahi deta.

Agar har instruction ek cycle stall kare, toh effective CPI aur throughput kya hoga?

CPI = 1 + 1 = 2, isliye throughput ideal ke muqable mein half ho jaata hai — har do cycles mein ek completion. Constant stalls clock period ko double karne jaisi hi cheez hain bina kisi design benefit ke.

Agar saare

k

stages ki delay identical ho aur

t_{r e g} = 0

ho, toh speedup kya hoga?

Exactly

k

— ideal upper bound.

\frac{\sum t _{i}}{m a x t _{i} + 0} = \frac{k t}{t} = k

. Koi bhi imbalance ya overhead isse neeche khenchta hai.

Agar branch misprediction rate 0% ho, toh branch ka CPI mein contribution kya hai?

Zero. Penalty term hai Branch-rate × Mispredict-rate × Penalty; zero mispredict factor poore term ko khatam kar deta hai, chahe branches kitni bhi frequent hon.

Ek pipeline jiska sabse slow stage delay bound ke bahar badhe, uska throughput kya hoga?

Yeh zero ke paas pahunch jaata hai. Kyunki

T_{p i p e} = max (t_{i}) + t_{r e g}

aur throughput

= 1/ T_{p i p e}

, unbounded slow stage ka matlab unbounded clock period aur vanishing completion rate — bottleneck poori tarah dominate karta hai.

t_{r e g} \to 0

aur infinite perfectly balanced stages ki limit mein, speedup ko kya cap karta hai?

Is idealized model mein kuch nahi — speedup

\to \infty

. Reality ise cap karti hai nonzero

t_{r e g}

, wire delays, aur badhte hazard penalties se, isliye real designs ~10–15 stages par plateau karte hain.

Recall Self-check: ek-sentence summary

Pipelining unchanged latency ko higher throughput ke liye trade karta hai instructions ko overlap karke; CPI measure karta hai ki real hazards tumhe ideal floor of 1 se kitna upar dhakelte hain, aur Time = Instr × CPI × $T_{cy c l e}$ sab kuch ek saath jod deta hai.