Data hazards and forwarding - bypassing: Question bank

5.2.6 · D5 · Hardware › Processor Datapath & Pipelining › Data hazards and forwarding - bypassing

Jinhe hum baar baar refer karte hain woh paanch stages hain $IF \to ID \to EX \to MEM \to WB$ : instruction fetch karo, decode karo aur registers padho, ALU ka kaam karo, memory touch karo, result wapas likho. Yeh order apne dimaag mein rakho — zyaadatar traps kab koi value paida hoti hai aur kab use padha jaata hai, isi mein chhupe hote hain.

True or false — justify karo

A RAW (Read-After-Write) hazard ka matlab hai ki ek baad wali instruction ek register ko tab padhne ki koshish karti hai jab pehli instruction ne use likha nahi hota

True — "read after write" woh program order hai jo hum chahte hain, aur hazard yeh hai ki pipeline read ko bahut jaldi hone deti hai, stale value pakad leta hai.

WAR aur WAW hazards ek simple in-order 5-stage pipeline mein common problems hain

False — kyunki har instruction ID mein padhhti hai aur WB mein likhti hai same fixed order mein, ek pehli instruction hamesha baad wali ke likhne se pehle padh leti hai; WAR/WAW tabhi dikkat karte hain jab instructions reorder ho sakein (dekho 5.3.02-Superscalar-out-of-order-execution).

Forwarding ek 5-stage pipeline mein saare stalls khatam kar deti hai

False — yeh ALU-to-ALU stalls khatam karti hai, lekin ek load apna data sirf MEM ke baad deta hai, isliye load ke turant baad ek dependent instruction ko exactly ek stall chahiye hoga (load-use hazard).

Jab destination register R0 ho (hardwired zero) to hazard ko safely ignore kiya ja sakta hai

True — R0 hamesha zero padhta hai kisi bhi "write" ke bawajood, isliye R0 ko target karne wala producer kuch nahi badalta aur na forwarding chahiye na stall.

Agar producing aur consuming instructions ke beech teen ya zyaada doosri instructions hain, toh forwarding ki zaroorat nahi

True — jab consumer EX pahunchta hai, producer WB finish kar chuka hota hai, toh register file ka normal read fresh value return karta hai.

Forwarding physically result ko register file mein normal se pehle likhti hai

False — forwarding value ko seedha ALU input mux tak route karti hai aur normal WB timing ko unchanged rehne deti hai; register file bypass hoti hai, speed up nahi hoti.

Stalling aur forwarding ek hi problem ko ek hi tarike se solve karte hain

False — dono RAW hazards fix karte hain, lekin stalling consumer ko delay karta hai jab tak data ready na ho, jabki forwarding data ko reroute karta hai taaki consumer ko wait hi na karna pade (ALU ops ke liye).

Forwarding unit EX stage mein rehti hai aur ALU input multiplexers ko control karti hai

True — yeh EX/MEM aur MEM/WB pipeline registers mein baithe destination registers ko EX mein aa rahi instruction ke source registers se compare karti hai, aur mux setting accordingly choose karti hai.

Error dhundho

"Ek single one-cycle bubble hamesha ALU-to-ALU RAW hazard fix karne ke liye kaafi hai."

Galat — result EX ke end mein produce hota hai lekin register file mein WB ke end mein aata hai, do stages baad, jabki consumer ID ke start mein padhta hai; back-to-back dependency ko forwarding ke bina do stall cycles chahiye, ek nahi.

"Hamesha MEM/WB register se forward karna chahiye jab usme zaroorat ki value ho, kyunki woh sabse settled result hai."

Galat — agar EX/MEM bhi usi register ko hold karta hai, toh EX/MEM zyaada recent producer hai aur use jeetna chahiye; purani MEM/WB value forward karna ek aisa result deliver karega jo program pehle hi overwrite kar chuka hai.

"Forwarding condition ko sirf EX/MEM.RegisterRd == ID/EX.RegisterRs check karna chahiye."

Galat — aapko yeh bhi require karna hoga ki RegWrite == 1 ho (producer actually ek register likhta hai) aur RegisterRd != 0 ho (zero register nahi); warna aap store/branch se garbage forward karoge ya ek phantom R0 write se.

"Load results ko turant agle instruction mein ALU results ki tarah forward kiya ja sakta hai."

Galat — ek load ka data MEM ke end tak available nahi hota, jo ALU result se ek stage baad hai; agle instruction ka EX shuru ho chuka hota hai, isliye hardware ko pehle ek cycle stall karna padta hai, phir MEM/WB se forward karta hai.

"Kyunki register file WB mein likhti hai aur ID mein padhti hai, 4 cycles peeche wali instruction mein bhi hazard ka risk hai."

Galat — split-phase register file ke saath (WB ke pehle aadhe mein write, ID ke doosre aadhe mein read), ek consumer jiska ID producer ke WB ke saath overlap karta hai fresh value padh leta hai; sirf closer distances (EX/MEM, MEM/WB) ko forwarding chahiye.

"Kyunki forwarding stall hatati hai, yeh clock cycle time chhoti kar deti hai."

Galat — forwarding EX path mein mux delay add karti hai aur critical cycle ko lamba kar sakti hai; yeh cycle count improve karti hai (kam stalls), cycle duration nahi.

"Do consecutive dependent instructions ka matlab hai hum EX/MEM se Rs aur Rt dono slots mein forward karte hain."

Galat — aap sirf us operand slot mein forward karte hain jo actually hazarded register ka naam leta hai; Rs aur Rt independently check hote hain, aur dono producer ke Rd se match kar bhi sakti hain aur nahi bhi.

Why questions

Classic in-order pipeline mein RAW hazards, WAR aur WAW par kyun dominant hain?

Kyunki reads (ID) aur writes (WB) har instruction ke liye ek fixed relative order mein hote hain, isliye anti- aur output-dependencies naturally resolve ho jaati hain; sirf "read-too-early" case (RAW) us ordering ke baad bhi bachta hai.

EX/MEM forwarding ko MEM/WB forwarding par priority kyun milni chahiye?

Jab dono pipeline registers same destination register hold karte hain, EX/MEM us younger instruction ka hai jo program order mein baad mein execute hui, aur consumer ko latest write dekhna chahiye, koi purani stale value nahi.

Load-use dependency ko forwarding bina kisi stall ke kyun nahi bacha sakti?

Load ki value sirf MEM stage ke baad exist karti hai, lekin dependent instruction ko yeh apne EX ke start mein chahiye — ek stage ka yeh timing gap sirf routing se close nahi kiya ja sakta, isliye ek single bubble unavoidable hai.

Hum destination register ko dono source operands (Rs aur Rt) ke against kyun check karte hain?

SUB R4, R1, R1 ya AND R6, R1, R7 jaisi instruction kisi bhi input ke through same producer par depend kar sakti hai; ALU ke do operand ports hain, isliye har ek independently forwarding ke liye eligible hona chahiye.

Hazard-detection logic register R0 par writes ko kyun exclude karta hai?

R0 hardwired zero hai, isliye isko "write" karna meaningless hai; ek supposed R0 result forward karna ek bogus value inject karega jahan consumer ko simply zero padhna chahiye tha.

Forwarding paths add karna CPI kyun reduce karta hai lekin datapath ko complicated kyun banata hai?

Kam stalls ka matlab cycles-per-instruction ke zyaada kareeb-1 hona, lekin har forwarding path ko extra wires, wider multiplexers, aur forwarding unit mein comparison logic chahiye — ek classic performance-vs-hardware-cost trade (dekho 5.2.09-Pipeline-performance-analysis).

Ek accha compiler kabhi kabhi ek stall kyun hata sakta hai jo hardware otherwise insert karta?

Producer aur consumer ke beech independent instructions ko reorder karke, compiler unki separation badata hai taaki value register file mein already ho jab padhi jaaye, load-use bubble ko poori tarah dodge karte hue (dekho 6.2.03-Compiler-optimization-techniques).

Edge cases

Kya hota hai jab producer R0 likhta hai aur consumer R0 padhta hai?

Koi hazard nahi aur koi forwarding nahi: R0 constant zero hai, isliye consumer hamesha bina kisi intervention ke sahi value padhta hai.

Kya hoga agar consumer instruction ek branch ho jise operand EX mein nahi, ID mein chahiye?

Standard EX-stage forwarding bahut late aati hai; branch operands pehle chahiye hote hain, isliye ya toh ID/branch-compare unit tak extra forwarding ya ek stall ki zaroorat hai — ek boundary jo 5.2.07-Control-hazardsand-branch-prediction mein spillover karti hai.

Kya hoga agar do consecutive instructions dono same destination register likhein, phir ek teesra use padhe?

Teesre ko doosre writer ki value milni chahiye; EX/MEM (doosre writer ko hold karta hai) MEM/WB (pehle writer ko hold karta hai) par priority leta hai, isliye zyaada recent result forward hota hai.

Kya hoga agar "producing" instruction ek store ya branch ho (RegWrite = 0)?

Koi register nahi likha jaata, isliye koi forwarding fire nahi hoti; forwarding condition mein RegWrite = 1 guard koi bhi false match on leftover Rd bits ko suppress karta hai.

Minimum instruction separation kya hai jis par forwarding ki kabhi zaroorat nahi hoti?

Roughly teen instructions apart (ya split-phase register file ke saath, woh point jahan consumer ka ID producer ke WB completion se pehle nahi hota) — iske aage ek plain register read kaafi hai.

Pipeline flush ya startup ke baad pehle instructions par kya hota hai, jab pipeline registers mein junk hota hai?

Un pipeline registers mein RegWrite/Rd validity bits clear kar diye jaate hain (ya bubbles RegWrite = 0 carry karte hain), isliye forwarding unit koi valid match nahi dekhti aur correctly kuch forward nahi karti.

Kya forwarding kuch bhi change karti hai ek aisi instruction ke liye jisme koi source register dependency nahi hai (e.g., ADDI R1, R0, 5)?

Nahi — sources R0 ya immediates ke barabar hone se koi destination-to-source match nahi hota, forwarding conditions false rehte hain, aur operands seedha register file/immediate field se aate hain.

Recall One-line self-test

Do back-to-back ALU instructions ek true dependency ke saath: forwarding ke bina kitne stalls chahiye? Forwarding ke saath? ::: Forwarding ke bina do stalls; EX/MEM forwarding ke saath zero stalls.

Recall One-line self-test

Ek load turant baad ek dependent ALU instruction ke: kya forwarding akele ise fix kar sakti hai? ::: Nahi — exactly ek stall pehle chahiye, phir MEM/WB se forward karo.