Structural hazards — Hinglish notes

5.2.5 · Hardware › Processor Datapath & Pipelining

Structural Hazard kya hota hai?

YEH KYUN hota hai: Pipelining ka goal hai multiple instructions ek saath execute karna, lekin hardware resources finite aur aksar shared hote hain. Cost aur complexity kam karne ke liye, designers sirf ek hi instance rakh sakte hain mehenga components ka (memory, multipliers). Jab do stages ko ek hi time par woh component chahiye, toh structural hazard ho jaata hai.

KYA hota hai: Pipeline mein ek stall daalna padta hai (jise bubble ya pipeline interlock bhi kehte hain). Jo instruction aage nahi badh sakti, woh ek ya zyada clock cycles tak resource free hone ka wait karti hai.

PERFORMANCE par ASAR: Har stall ek clock cycle waste karta hai jisme koi naya kaam nahi hota. Agar hazard baar baar aata rahe, toh effective CPI ideal 1.0 se zyada ho jaata hai.

Common Causes aur Examples

1. Single-Port Memory (Sabse Common)

PROBLEM YEH HAI: Classic MIPS mein alag instruction aur data caches hote hain, lekin ek aise system ko socho jisme sirf ek unified memory ho:

Cycle 1: Instruction A, IF (Instruction Fetch) mein hai, memory read kar rahi hai
Cycle 4: Instruction D, MEM (Memory access) mein hai, data read/write kar rahi hai

Agar dono ek saath memory access karne ki koshish karein, toh structural hazard ho jaata hai.

Worked example Single Memory Port Conflict

Pipeline timeline (simplified 5-stage: IF, ID, EX, MEM, WB):

Time:    12    3    4    5    6
I1:     IF   ID   EX  MEM   WB
I2:          IF   ID   EX  MEM   WB
I3:               IF   ID   EX  MEM   WB
I4:                    IF  STALL  IF   ID  ...
               ↑
                     Conflict! I1 in MEM, I4 in IF

Stall kyun?: Cycle 4 mein, I1 ko data access ke liye memory chahiye (MEM stage) aur I4 ko instruction fetch ke liye memory chahiye (IF stage). Sirf ek hi proceed kar sakta hai.

Fix: I4, IF mein stall karta hai, ek cycle wait karta hai. I1 apna memory access complete karta hai, phir I4 cycle 5 mein apni instruction fetch karta hai.

Performance impact: CPI badhta hai. Agar 30% instructions loads/stores hain, aur pipeline depth 5 hai, toh hume stall milega ~har 5/1.3 ≈ 4 instructions = 25% performance loss.

YEH DESIGN KYUN EXIST KARTA HAI: Dual-ported memory (alag instruction aur data ports) mehenga hota hai. Kuch embedded systems cost/power bachane ke liye single-port memory use karte hain. Harvard architecture (alag instruction/data memories) is hazard se bachta hai lekin zyada hardware maangta hai.

2. Insufficient Functional Units

Worked example Multiple Stages ke Beech Shared Single ALU

Kuch processors ALU ko EX stage (arithmetic) aur IF stage (PC increment: PC = PC + 4) dono mein use karte hain.

Conflict scenario:

Cycle 3: ADD instruction EX (needs ALU for addition)
Cycle 3: Next instruction in IF (needs ALU to compute PC+4)

Resolution: PC increment ke liye ek alag adder provide karo (sasta, simple adder), ya IF ko stall karo jab tak EX complete na ho jaaye.

Modern solution: Dedicated PC incrementer hardware. Ek 32-bit adder ki cost frequent stalls se hone wale performance loss ke comparison mein bahut kam hai.

3. Register File Ports

Read ports: ID stage do source registers read karta hai (jaise, rs, rt)
Write port: WB stage ek destination register likhta hai (rd)

Hazard tab agar: Ek cycle mein 2 se zyada reads ya 1 se zyada writes ki koshish ho.

Mathematical Analysis: Performance Impact

Chaliye effective CPI derive karte hain jab structural hazards aate hain.

YEH FORMULA KYUN?: Har stall ek cycle add karta hai jisme pipeline koi useful kaam nahi karta. Hazards ki frequency instruction mix (kitni baar memory access karte hain, specific units use karte hain) aur pipeline structure (kitne stages conflict kar sakte hain) par depend karti hai.

Scratch se Derivation:

Ideal throughput: Har cycle mein ek instruction complete → CPI = 1.0
Stall insertion: Jab hazard aata hai, ek "bubble" (NOP) insert karo. Jo instruction conflicting stage mein enter karne wali thi, woh ek cycle wait karti hai.
Stalls count karna: Agar $p$ probability hai ki hazard har instruction par aata hai, aur har hazard $s$ cycles cost karta hai, toh: $Average stalls per instruction = p \times s$
Total CPI: $CPI = 1 + p \times s$

Memory hazards ke liye $p = f_{mem}$ aur $s = 1$ ke saath: $CPI = 1 + f_{mem}$

Structural Hazards ke Solutions

Formula Resolution Strategies

Hardware resources add karo (hazard eliminate karo)

Dual-ported memory ya alag I-cache/D-cache
Multiple functional units (2 ALUs, dedicated multiplier)
Zyada register file ports Cost: $↑$ Silicon area, power, design complexity

Pipeline interlock logic (detect karo aur stall karo)

Hardware conflicts detect karta hai, automatically stalls insert karta hai
Control logic: Agar (stage A ko resource R chahiye) AUR (stage B ko resource R chahiye), toh stage B ko stall karo Cost: $↑$ Control complexity, $↓$ Performance

Instructions schedule karo (conflicts avoid karo)

Compiler/programmer instructions reorder karta hai taaki simultaneous resource access na ho
Pipeline structure ki knowledge chahiye

Cost: Hamesha possible nahi hota; dependencies se limited

Lower performance accept karo (kuch mat karo)

Rare hazards ke liye, kabhi-kabhi stalling acceptable ho sakta hai
Trade-off: performance vs. cost

KONSA CHOOSE KAREIN?:

High-performance processors: Hardware add karo (cost, performance se justify hoti hai)
Embedded systems: Occasional stalls tolerate karo (area/power critical hai)
Modern CPUs: Separate I/D caches standard hain; structural hazards zyaadatar eliminate ho gaye hain

Structural vs. Data vs. Control Hazards

Recall Ek 12-saal ke bachche ko explain karo

Tum apne dost ke saath video game khel rahe ho, ek single controller pe baari-baari. (Controller processor mein ek "resource" ki tarah hai.)

Structural hazard: Tumhe dono ko controller ki zaroorat hai bilkul ek hi time par buttons press karne ke liye. Kyunki sirf ek controller hai, tumhe se ek ko wait karna padega. Yahi structural hazard hai—jitne log chahein utne controllers (hardware) nahi hain abhi.

Data hazard: Tumhe apni baari lene se pehle dekhna hai ki tumhare dost ne kya kiya (jaise unke move dekhne ka wait karna phir apna move karne ke liye). Yeh tumhare beech order aur information pass hone ke baare mein hai.

Control hazard: Tum dekh rahe ho ki tumhara dost boss ko beat karta hai ya nahi, taaki decide kar sako ki retry karni chahiye ya next level pe jaana chahiye. Yeh decisions ke baare mein hai jo decide karta hai tum aage kya karte ho.

Structural hazards sabse simple hain: bas jab sabko ek saath "cheez" chahiye hoti hai toh enough "cheez" nahi hoti!

| Hazard Type | Cause | Solution | |-------------|----------| | Structural | Hardware resource conflict | Resources add karo, stall karo | | Data | Instruction pichle result par depend karti hai | Forwarding, stall | | Control | Branch outcome unknown | Prediction, stall |

KEY INSIGHT: Structural hazards only hardware limitations se aate hain, instruction sequence se nahi. Data aur control hazards unlimited hardware ke saath bhi hote hain—yeh dependencies aur decisions ke baare mein hain. Structural hazards enough paison se eliminate ho sakte hain (har resource duplicate karo), lekin data/control hazards algorithm ke liye fundamental hain.

Common Mistakes aur Steel-Manning

Common mistake Mistake 2: "Bubble add karna ek clock cycle bilkul waste kar deta hai"

Kyun sahi lagta hai: Jo instruction stall karti hai woh bubble cycle mein koi kaam nahi karti, isliye lagta hai "wasted time" hai.

Sach: Pipeline doosri instructions ke liye kaam karta rehta hai. Stall ek instruction ko aage badhne se rokta hai, lekin usse aage ki instructions progress karti rehti hain. Throughput kam ho jaata hai (CPI > 1), lekin pipeline poori tarah idle nahi hoti.

Example:

Before stall:  I1[MEM] I2[EX] I3[ID] I4[IF]
Stall cycle:   I1[WB]  I2[MEM] I3[EX] I4[stall] (I4 waits)
After stall:   done    I2[WB]  I3[MEM] I4[ID]   (I4 resumes)

Fix: Stall throughput kam karta hai (kam instructions per second) lekin poori pipeline freeze nahi karta. Socho jaise highway ki ek lane ruk gayi ho jabki baaki chalta rahe.

Worked Example: Hazard Scenario Analyze Karna

Worked example Full Pipeline Trace with Structural Hazard

Setup: 5-stage pipeline (IF, ID, EX, MEM, WB), single unified memory (alag I/D caches nahi hain).

Instruction sequence:

I1: LW  R1, 0(R2)    # Load from memory
I2: ADD R3, R1, R4
I3: SUB R5, R3, R6
I4: SW  R5, 0(R7)    # Store to memory
I5: AND R8, R5, R9

Pipeline timeline (clock cycles):

    1    2    3    4    5    6    7    8    9
I1: IF   ID   EX  MEM   WB
I2:      IF   ID   EX  MEM   WB
I3:           IF   ID   EX  MEM   WB
I4:              STALL  IF   ID   EX  MEM   WB
I5:                         IF   ID   EX  MEM   WB

Cycle 4 mein stall kyun?

I1 MEM stage mein hai (cycle 4): data load karne ke liye memory chahiye
I4 IF stage mein hona chahiye (cycle 4): instruction fetch karne ke liye memory chahiye
Conflict: Sirf ek memory access per cycle allowed hai
Resolution: I4 stall karta hai, cycle 5 mein apni instruction fetch karne ka wait karta hai

Performance impact:

Ideal cycles: 5 instructions, ideal CPI = 1.0 → 9 cycles total (5 + pipeline depth - 1 = 5 + 4)
Actual cycles: 10 cycles (ek extra stall)
Actual CPI: 10/5 = 2.0 (bahut bura! sirf ek stall se 100% overhead)

Ruko, yeh calculation galat hai. Chaliye recalculate karte hain:

Ideal: Pehli instruction 5 cycles leti hai, phir har cycle mein ek → total = 5 + (5-1) = 9 cycles
Actual: 9 + 1 stall = 10 cycles
CPI: 10/5 = 2.0? Nahi, ruko—CPI calculation:
Total cycles = 10
Total instructions = 5
CPI = 10/5 = 2.0 sahi hai, lekin yeh ek stall ke liye zyada lagta hai.

Actually, mujhe dobara sochna hoga. Chaliye zyada carefully trace karte hain: Correct timeline:

    1    2    3    4    5    6    7    8    9
I1: IF   ID   EX  MEM   WB
I2:      IF   ID   EX  MEM   WB
I3:           IF   ID   EX  MEM   WB
I4:                IF   ID   EX  MEM   WB
               ↑ Conflict with I1[MEM] in cycle 4

Cycle 4 mein: I1 MEM mein hai, I4 IF karna chahta hai. I4 ko stall karo.

    1    2    3    4    5    6    7    8    9   10
I1: IF   ID   EX  MEM   WB
I2:      IF   ID   EX  MEM   WB
I3:           IF   ID   EX  MEM   WB
I4:              STALL  IF   ID   EX  MEM   WB
I5:                         IF   ID   EX  MEM   WB

Total cycles: 9 (I5[WB] cycle 9 mein complete hoti hai) Ruko, chaliye count karte hain: I5[WB] cycle 9 mein matlab 9 cycles total.

Hmm, lekin humara ek stall tha. Chaliye phir se trace karte hain:

Stall ka matlab hai I4 aur uske baad ki saari instructions 1 cycle shift ho jaati hain:

    1    2    3    4    5    6    7    8    9   10
I1: IF   ID   EX  MEM   WB
I2:      IF   ID   EX  MEM   WB
I3:           IF   ID   EX  MEM   WB
I4:                    IF   ID   EX  MEM   WB    (stall se shift)
I5:                         IF   ID   EX  MEM   WB

Ruko, yeh abhi bhi galat lag raha hai. Jab I4, cycle 4 mein stall karta hai, toh woh IF nahi karta. Woh cycle 5 mein IF karta hai:

    1    2    3    4    5    6    7    8    9   10
I1: IF   ID   EX  MEM   WB
I2:      IF   ID   EX  MEM   WB
I3:           IF   ID   EX  MEM   WB
I4:               X    IF   ID   EX  MEM   WB
I5:                         IF   ID   EX  MEM   WB

X = stall (koi progress nahi). Ab I5 cycle 5 mein bhi IF nahi kar sakta kyunki I4 IF kar rahi hai. Toh I5 wait karta hai:

    1    2    3    4    5    6    7    8    9   10
I1: IF   ID   EX  MEM   WB
I2:      IF   ID   EX  MEM   WB
I3:           IF   ID   EX  MEM   WB
I4:               X    IF   ID   EX  MEM   WB
I5:                    X    IF   ID   EX  MEM   WB

Ruko, yeh cascade ho raha hai? Chaliye alag tarike se socho.

Sahi samajh: Jab I4, cycle 4 mein stall karta hai, pipeline I4 ke aage ek bubble insert karta hai. I4 aage nahi badhta, toh I5 bhi nahi badhta:

    1    2    3    4    5    6    7    8    9
I1: IF   ID   EX  MEM   WB
I2:      IF   ID   EX  MEM   WB
I3:           IF   ID   EX  MEM   WB
I4:                IF   ID   EX  MEM   WB
I5:                         IF   ID   EX  MEM   WB

Cycle 4 mein, I4 ka IF block ho jaata hai. I4 "IF mein enter hone ke wait" mein reh jaata hai. Cycle 5 mein, I1 MEM exit karta hai, memory free ho jaati hai, I4 IF karta hai. Total time: 9 cycles.

CPI calculation:

5 instructions 9 cycles mein: CPI = 9/5 = 1.8 Hazard ke bina: 5 instructions 9 cycles mein (ruko, yeh same hai!)

Chaliye ideal case recalculate karte hain:

Pehli instruction: 5 cycles (IF cycle 1, WB cycle 5 mein)
Baad ki instructions: har cycle mein ek (pipelining)
5 instructions ka total: 5 + (5-1) = 9 cycles Toh ideal bhi 9 cycles hai? Phir stall penalty kahan hai?

AH! Main samajh gaya: Mere timeline mein, I4 ka cycle 4 mein IF karna already ideal case hai (koi structural hazard nahi). Chaliye hazard ke saath dobara karte hain:

WITH structural hazard (I1[MEM], cycle 4 mein I4[IF] se conflict karta hai):

    1    2    3    4    5    6    7    8    9   10
I1: IF   ID   EX  MEM   WB
I2:      IF   ID   EX  MEM   WB
I3:           IF   ID   EX  MEM   WB
I4:              (stall) IF   ID   EX  MEM   WB
I5:                          IF   ID   EX  MEM   WB

Total: 10 cycles. CPI = 10/5 = 2.0. WITHOUT hazard (alag I/D memory):

    1    2    3    4    5    6    7    8    9
I1: IF   ID   EX  MEM   WB
I2:      IF   ID   EX  MEM   WB
I3:           IF   ID   EX  MEM   WB
I4:                IF   ID   EX  MEM   WB
I5:                     IF   ID   EX  MEM   WB

Total: 9 cycles. CPI = 9/5 = 1.8.

Penalty: 1 cycle stall, 11% performance loss (9/10 = 0.9 speedup).

Connections

Pipelining Fundamentals - Structural hazards teen hazard types mein se ek hain
Data Hazards - Resource conflicts vs. data dependencies compare karo
Control Hazards - Branch prediction vs. hardware duplication trade-offs
Memory Hierarchy - Alag I/D caches memory structural hazards eliminate karte hain
Superscalar Processors - Multiple issue mein bahut zyada resources chahiye, zyada structural hazards
Pipeline Stalls - Saare hazard types handle karne ka mechanism
Instruction-Level Parallelism - Resource constraints ILP extraction ko limit karte hain

#flashcards/hardware

Structural hazard kya hota hai? :: Ek pipeline hazard jo resource conflicts se hota hai jab multiple instructions ko ek hi saath ek hi hardware component chahiye (jaise memory, ALU, register ports).

Basic pipelined processors mein sabse common structural hazard ka cause kya hai?

Single-port unified memory: instruction fetch (IF stage), data access (MEM stage) se conflict karta hai.

Structural hazard CPI ko kaise affect karta hai?

Yeh CPI ko 1.0 se upar le jaata hai stalls insert karke. CPI_actual = CPI_ideal + (frequency of hazard × stall penalty).

Structural hazards ke do main solutions kya hain?

(1) Hardware resources add karo (memory, functional units, ports duplicate karo) conflicts eliminate karne ke liye. (2) Shared resource ka access serialize karne ke liye pipeline stalls insert karo.

Modern high-performance processors mein structural hazards kyun kam hain?

Yeh alag instruction aur data caches (Harvard architecture), multiple functional units, aur multi-ported register files use karte hain, conflicts avoid karne ke liye resources duplicate karte hain.

Structural hazard, data hazard se alag kaise hai?

Structural: hardware resource conflict (enough hardware nahi). Data: instruction dependency (result ka wait). Structural hardware add karke eliminate ho sakta hai; data hazards algorithmic hain.

Ek single structural hazard stall ki performance penalty kya hai?

Har stall mein ek clock cycle. Agar stalls frequent hain (jaise 30% instructions), CPI 1.0 se 1.3 tak badh sakta hai, ~23% performance kho ke.

Ek designer kab structural hazards accept kar sakta hai hardware add karne ki jagah?

Cost/power-sensitive embedded systems mein, ya jab hazard itna rare ho ki performance loss, hardware duplicate karne ki cost ke comparison mein acceptable ho.