4.3.22
YEH KYA HAI? Jab ek wafer fabricate ho jaati hai aur individual dies mein dice ho jaati hai, tab har bare silicon die ko package karna padta hai: mechanically protect karo, electrically bahar ki duniya se connect karo, aur heat shed karne ka ek raasta do. Wire bonding aur flip-chip — yeh do dominant tarike hain jin se die ke tiny on-chip pads aur package leads ke beech electrical connections bante hain.
Ek bare die bilkul ek spider's web jaise hai jo glass se bani ho: transistors microns wide hote hain, bond pads ~50–100 µm ke hote hain, aur ek human fingertip ya ek bhatak'ta hua paani ka droplet use destroy kar sakta hai. Package chaar kaam karta hai:
Electrical connection — signals aur power andar/bahar route karo.Mechanical protection — handling, moisture, vibration se encapsulation.Heat removal — junction se ambient tak ek thermal path do.Fan-out — ~50 µm die pads ko ~0.5 mm PCB pitch par spread karo taaki ek board pe actually solder ho sake.
Die : wafer se kata hua individual chip.Bond pad (I/O pad) : die surface par connection ke liye metal landing spot.First-level interconnect : die → package (wire bond YA flip-chip bumps).Second-level interconnect : package → PCB (leads, balls, pins).
Sewing ki tarah imagine karo: ek patla gold ya copper ka dhaga die ke pad se upar aur dusri taraf lead frame ya substrate tak tanka jaata hai. Die face-up baithti hai, apni peeth se chipkayi hui, aur wires sirf perimeter ke saath pads tak pahunchte hain.
Die bond pads ko package leads se fine (~15–33 µm) gold, copper, ya aluminium wires ka istemal karke connect karna, jinhein heat + pressure + ultrasonic energy se joda jaata hai.
Do flavours:
Ball bonding (thermosonic): ek spark wire tip ko ball mein pighlata hai, pad par press kiya jaata hai ("first bond"), phir ek "stitch/wedge" doosre end ko seal karta hai. Tez, Au/Cu ke liye common.Wedge bonding (ultrasonic): wire ko bina ball ke drag aur press kiya jaata hai; Al, coarse pitch, RF/power ke liye use hota hai.
Edge se wires seene ki jagah, hum tiny solder bumps die ke poore face par ugaate hain, phir die ko ulta flip karte hain aur substrate par rakhte hain taaki har bump ek matching pad par land kare. Koi wires nahi — connection seedha neeche jaata hai.
Definition Flip-chip (C4 = Controlled Collapse Chip Connection)Die ko face-down ek substrate par solder bumps ke area array ke zariye mount karna, reflow karke seedhe vertical joints banaye jaate hain. Phir underfill epoxy die aur substrate ke beech wicked jaati hai.
Intuition Flip-chip ke teen killer advantages
I/O count : area beats perimeter (upar dekho).Electrical performance : ek bump ~0.1 mm tall hota hai vs ek wire ~1–3 mm long ⇒ bahut kam parasitic inductance L Thermal/back-side access : die ki peeth ab upar face karti hai, heat spreader/heatsink bond karne ke liye free.
Worked example 1) I/O crossover die sizeSame pitch p ( L / p ) 2 > 4 L / p ⇒ L / p > 4 ⇒ L > 4 p Yeh step kyun? Humne quadratic > linear set kiya aur L / p kisi bhi die ke liye jo 4 pad-pitches se zyada wide ho, area array jeet'ta hai — real chips mein practically hamesha.
Worked example 2) Modern CPU ke liye bump countDie 20 mm × 20 mm, bump pitch 0.15 mm.
N = ( 20/0.15 ) 2 ≈ 13 3 2 ≈ 17 , 700 Yeh step kyun? Whole-face 2-D grid ⇒ linear bump count ko square karo. Wire bonding sirf 4 ( 20 ) /0.15 ≈ 533
Worked example 3) Ground-bounce comparisond i / d t = 0.5 A/ns = 5 × 1 0 8 A/s L = 2 L = 0.05 V = 2 × 1 0 − 9 × 5 × 1 0 8 = 1.0 0.025 Yeh step kyun? V = L d i / d t zaroor flip-chip use karna chahiye.
Common mistake "Wire bonding obsolete ho gayi hai."Kyun sahi lagta hai: flip-chip mein zyada I/O aur better speed hai, toh yeh lagta hai strictly superior hai. Fix: wire bonding sasti hai, koi bumping/underfill step nahi chahiye, low pin counts tolerate karta hai, aur cheap/medium chips (microcontrollers, LEDs, sensors) mein dominant hai. Superior ≠ har product ke liye cost-effective.
Common mistake "Flip-chip mein die face-up hoti hai."Kyun sahi lagta hai: har doosra package jise hum picture karte hain (DIP) mein die face-up hoti hai. Fix: flip-chip literally flip karta hai — active face substrate ki taraf neeche point karta hai; peeth upar face karti hai (cooling ke liye bahut achha).
Common mistake "Underfill optional glue hai."Kyun sahi lagta hai: solder bumps pehle se hi die ko hold karte hain. Fix: silicon aur substrate ke alag-alag CTE (thermal expansion) hote hain. Heating/cooling par, mismatch bumps ko shear karta hai; underfill epoxy us stress ko redistribute karta hai aur reliability ke liye zaruri hai.
Common mistake "Zyada heat = hamesha better bond."Kyun sahi lagta hai: heat diffusion drive karta hai. Fix: bahut zyada heat pads ko oxidize karta hai, brittle intermetallics banata hai (jaise Au–Al "purple plague"), aur die warp ho jaati hai. Bonding teen energies ka balance hai, koi heat maximum nahi.
Recall Answers cover karo — kya tum inhe reconstruct kar sakte ho?
Package ke chaar kaam? → connect, protect, cool, fan-out.
Flip-chip quadratically scale kyun karta hai? → area array vs 1-D perimeter.
Thermosonic bonding ki teen energies? → thermal, mechanical, ultrasonic.
Underfill kyun? → CTE mismatch stress relief.
Wire-bond max I/O ka formula? → 4 L / p
Recall Feynman: ek 12-saal ke bachche ko explain karoEk computer chip ek tiny glass tile hai jo invisible wiring se dhaki hui hai, lekin yeh itni chhoti aur fragile hai ki kuch bhi plug in nahi kar sakte. Toh hum ise ek "ghar" (package) mein rakhte hain. Electricity andar aur bahar aane dene ke liye, hum ya toh tile ke edge se ghar ke legs tak patale gold ke dhaage seente hain (wire bonding) — lekin tum sirf edge ke aas-paas see sakte ho, toh bahut saare dhaage fit nahi hote. YA hum tile ke poore face par tiny solder blobs lagate hain, use ulta flip karte hain , aur neeche press karte hain taaki har blob ek pad se touch kare (flip-chip). Kyunki tum poora face use karte ho, sirf edge nahi, tum bahut zyada connections le sakte ho — aur tiny blobs electricity ko lambe dhaagon se zyada tezi se flow karne dete hain.
"Wires ring the Rim, Bumps fill the Board."
Wire-bond = R im (perimeter, 4 L / p B oard/whole face (( L / p ) 2 C4 = C ontrolled C ollapse C hip C onnection.
Wafer Dicing — individual dies produce karta hai jo package hote hain.Thermal Management and Heat Sinks — flip-chip ka exposed back ise enable karta hai.Signal Integrity and Parasitic Inductance — V = L d i / d t Ball Grid Array (BGA) — flip-chip parts ke liye ek common second-level interconnect.Coefficient of Thermal Expansion (CTE) Mismatch — underfill kyun exist karta hai.Intermetallic Compounds and Bond Reliability — joint ki metallurgy.
IC package ke chaar functions kya hain? Electrical connection, mechanical protection, heat removal, aur fan-out (die se PCB tak pitch translation).
Wire bonding mein die kaise baithti hai aur connections kahan hote hain? Face-up, apni peeth se chipkayi hui; connections sirf perimeter pads ke saath.
Flip-chip mein die kaise baithti hai? Face-down, active surface substrate ki taraf, solder bumps ke area array se connected.
Perimeter wire bonding ke liye max I/O? N = 4L/p (die side L mein linear).
Area-array flip-chip ke liye max I/O? N = (L/p)^2 (die side L mein quadratic).
Kis die size ke upar flip-chip wire bonding se jeet'ta hai (same pitch)? Jab L > 4p (solving (L/p)^2 > 4L/p).
Thermosonic bond banane mein teen energies kya hain? Thermal (heat), mechanical (force), aur ultrasonic (oxide remove karne ke liye vibration).
C4 ka full form kya hai? Controlled Collapse Chip Connection (solder-bump flip-chip method).
Flip-chip electrically wire bonding se tez kyun hai? Chhote (~0.1 mm) bumps mein lambe (~1–3 mm) wires se bahut kam parasitic inductance/resistance hoti hai, V = L·di/dt noise reduce hoti hai.
Underfill kya hai aur yeh kyun zaruri hai? Epoxy jo die aur substrate ke beech wicked jaati hai; yeh CTE mismatch se stress redistribute karta hai, solder-bump fatigue rokta hai.
Ball bond vs wedge bond? Ball = spark-formed ball + stitch, thermosonic, Au/Cu; wedge = koi ball nahi, ultrasonic pressing, Al/coarse pitch ke liye use hota hai.
Sirf aur heat add karke better wire bonds kyun nahi ban sakte? Zyada heat pads oxidize karta hai aur brittle intermetallics banata hai (jaise Au–Al 'purple plague') aur die warp ho jaati hai.
E_bond = thermal + mechanical + ultrasonic
N = 4L / p perimeter limit
Face-down, area-array bumps
