Silicon wafer production (Czochralski process)

4.3.1 · Hardware › Semiconductor Fabrication

YE sab kyun zaroori hai?

Single crystal kyun? Grain boundaries aur dislocations charge trap karte hain aur current leak karte hain. Billions of identical transistors ko identical, defect-free atomic terrain chahiye.

YE kaise kaam karta hai — step by step

Figure — Silicon wafer production (Czochralski process)

Growth sequence (HER step kyun):

Stage	Action	Kyun
Seeding	Seed daalo, tip ko melt back karo	Seed ke surface defects hatata hai
Necking (Dash neck)	Tezi se kheencho → patla (~3 mm) neck	Dislocations ko bhagaa deta hai — wo surface pe glide karke gayab ho jaate hain
Shouldering	Pull slow karo / cool karo	Diameter target tak phail jaata hai
Body	Constant pull + rotation	Lambi uniform-diameter cylinder ugao
Tail	End mein speed badhaao	Thermal-shock dislocations se bachao

Key physics — heat balance se pull rate derive karna

Formula Maximum pull rate — freezing interface pe energy balance se

KYA: Solid–liquid interface pe, energy in = energy out.

Scratch se Derivation: Us flat interface ko consider karo jahan liquid solid ban jaati hai. Per unit time, crystal ki length $v$ (cross-section $A$ ) solidify hoti hai. Mass rate $= ρ A v$ .

Freezing se generate hui heat (latent heat $L$ per unit mass): $\dot{Q}_{gen} = L ρ A v$

Solid crystal ke upar conduct hui heat. Fourier's law, thermal conductivity $k_{s}$ aur axial temperature gradient $\frac{d T}{d x}$ ke saath: $\dot{Q}_{cond} = k_{s} A \frac{d T}{d x}$

Steady state: (upper bound ke liye melt se aane wali heat neglect karte hain) $L ρ A v_{m a x} = k_{s} A \frac{d T}{d x}$ $A$ cancel karo aur solve karo: $v_{m a x} = \frac{k _{s}}{L ρ} \frac{d T}{d x}$

KAISE padho: zyada tezi se cooling (bada gradient) ⇒ tezi se kheeencho. Zyada latent heat/density ⇒ dheere kheeencho. Real growth mein quality ke liye $v < v_{m a x}$ use hoti hai.

Formula Dopant incorporation — segregation coefficient

KYU: Impurities solid mein melt ke same concentration pe nahi jaati. Solid zyaadatar dopant ko wapis liquid mein "reject" kar deta hai.

Definition (equilibrium se): interface pe, $k_{0} = \frac{C _{s}}{C _{l}}$ jahan $C_{s}$ = solid mein dopant conc., $C_{l}$ = liquid mein. Si mein boron ke liye $k_{0} \approx 0.8$ ; phosphorus ke liye $\approx 0.35$ .

Consequence — Scheil equation (derivation): Maan lo melt mass fraction se shuru hoti hai, aur $X$ = already solidified melt ka fraction. Thoda sa $d X$ freeze karne pe dopant conservation: $d (melt mein dopant) = - C_{s} d X, C_{s} = k_{0} C_{l}$ $C_{l} = \frac{( melt mein dopant )}{( 1 - X )}$ ke saath, integrate karne pe normal freezing / Scheil relation milti hai: $C_{s} (X) = k_{0} C_{0} (1 - X)^{k_{0} - 1}$ jahan $C_{0}$ initial melt concentration hai.

KAISE padho: kyunki $k_{0} < 1$ hai, exponent $k_{0} - 1 < 0$ hai, toh jaise-jaise zyada boule freeze hoti hai $C_{s}$ badhti jaati hai → tail end top se zyada heavily doped hota hai. Isse boule ke along axial resistivity variation hoti hai.

Worked examples

Common mistakes (Steel-manned)

Recall (khud test karo)

Recall Feynman: ek 12-saal ke bacche ko explain karo (click to reveal)

Socho ek badi pot mein pighla hua, super-clean sand-metal (silicon) glowing hot hai. Tum usme ek chhota sa perfect ice-cube-jaisa crystal ek dhage pe daalo aur dheere-dheere upar kheencho spin karte hue. Garam liquid uske upar freeze ho jaata hai aur iske neat pattern ko exactly copy karta hai, jaise ek growing icicle — lekin ek giant, perfectly ordered wala. Tum kheencho kheencho jab tak ek bada shiny cylinder na mil jaaye. Phir isse salami ki tarah thin round wafers mein slice karo, aur har slice computer chip ka base ban jaata hai. Dheere kheencha zaroori hai, kyunki freezing se heat nikalni padti hai jise dhage ke upar se nikalne mein time lagta hai.

Recall Quick self-quiz

Patla neck kyun? ::: Dislocations ko surface pe glide out karne deta hai (Dash necking) → dislocation-free crystal body.
Maximum pull rate kya set karta hai? ::: Heat balance: released latent heat conduct away honi chahiye → $v_{m a x} = \frac{k _{s}}{L ρ} \frac{d T}{d x}$ .
Boule ke tail ki resistivity alag kyun hoti hai? ::: Segregation ( $k_{0} < 1$ ) dopant ko shrinking melt mein concentrate karta hai: $C_{s} = k_{0} C_{0} (1 - X)^{k_{0} - 1}$ .

Flashcards

What crystal form must a chip substrate have and why?

Single-crystal (monocrystalline) — grain boundaries carriers ko scatter karte hain aur current leak karte hain, transistors kharaab ho jaate hain.

In the Czochralski process, what is dipped into the melt?

Ek seed crystal jiska defined orientation ho (jaise ⟨100⟩) ek rotating pull-rod pe.

What is the boule/ingot?

Seed ko melt se kheench ke ugaaya gaya large single-crystal cylinder.

State the max pull-rate formula and derive its origin.

v_{m a x} = \frac{k _{s}}{L ρ} \frac{d T}{d x}

; generated latent heat (

L ρ A v

) ko conducted away heat (

k_{s} A d T / d x

) ke saath balance karne se.

What is the segregation coefficient

k_{0}

k_{0} = C_{s} / C_{l}

, interface pe solid mein dopant conc. ka liquid se ratio (B≈0.8, P≈0.35).

State the Scheil (normal freezing) equation.

C_{s} (X) = k_{0} C_{0} (1 - X)^{k_{0} - 1}

, X = solidified fraction.

Why does dopant concentration rise along the boule?

Kyunki

k_{0} < 1

hai, solid dopant ko shrinking melt mein reject karta hai, baad mein freeze hone wala material enrich hota jaata hai.

Purpose of the Dash neck?

Patla fast-pulled neck dislocations ko glide out hone deta hai → dislocation-free crystal body.

Why do seed and crucible rotate oppositely?

Thermal/flow field ko axisymmetric banane ke liye → flat interface + uniform radial doping.

Silicon melting point?

1414 °C.

Where does oxygen in CZ silicon come from and is it all bad?

Fused-quartz (SiO₂) crucible se dissolve hoti hai; controlled O metals ko getter karta hai aur wafers ko strong banata hai, lekin excess thermal donors cause karta hai.

CZ vs Float-Zone regarding purity?

FZ crucible se bachta hai → less oxygen, purer/higher-resistivity, lekin CZ bade diameters ke liye sasta hai.

Connections

Semiconductor Fabrication (parent chapter)
Float-Zone crystal growth — crucible-free alternative
Doping and Resistivity — $C_{s}$ resistivity kaise set karta hai
Wafer slicing and polishing — boule ke baad ka agla step
Crystal defects and dislocations — jo necking eliminate karta hai
Fourier's law of heat conduction — pull-rate derivation mein use hota hai
Phase diagrams and segregation — $k_{0}$ ka origin