Transconductance (gm): Worked examples — Hardware deep dive

This page is the drill hall for Transconductance (gm). The parent note built the two master formulas — BJT $g_{m} = I_{C} / V_{T}$ and MOSFET $g_{m} = k V_{o v} = 2 I_{D} / V_{o v} = 2 k I_{D}$ . Here we throw every kind of question at them: both device families, every regime, degenerate/zero inputs, limiting behaviour, a real-world word problem, and a nasty exam twist. If a scenario can happen, you will see it worked below.

The scenario matrix

Every question about $g_{m}$ falls into one of these cells. The worked examples below are labelled with the cell(s) they cover, and together they hit all of them.

Cell	What varies	Example(s)
A. BJT, plain	Given $I_{C}$ , find $g_{m}$	Ex 1
B. BJT, temperature	$V_{T}$ changes with $T$	Ex 2
C. MOSFET, from $V_{o v}$	Given $k, V_{o v}$ (or $V_{GS}, V_{t h}$ )	Ex 3
D. MOSFET, from $I_{D}$	Given $I_{D}$ , use $2 k I_{D}$	Ex 4
E. Same current, BJT vs FET	Fair comparison at equal bias	Ex 5
F. Fixed $I_{D}$ , sweep $V_{o v}$	The counter-intuitive tradeoff	Ex 6
G. Degenerate / zero / subthreshold / PFET	$I_{C} \to 0$ , $V_{o v} \to 0$ , weak inversion, sign of $g_{m}$	Ex 7
H. Real-world word problem	Design a gain stage backwards	Ex 8
I. Exam twist	Ratio $I_{C} / V_{B E}$ trap + scaling law	Ex 9

Two figures support the geometric cells: Figure 1 (the exponential slope — why the BJT derivative is what it is) and Figure 2 (the $g_{m}$ -vs- $V_{o v}$ curves at fixed current, cell F).

Figure 1.

Figure 1 is the whole reason $g_{m}$ is a derivative and not a ratio. The blue curve is $I_{C} = I_{S} e^{V_{B E} / V_{T}}$ , where $V_{B E}$ (defined above) is the base-emitter voltage and sits near $0.7 V$ at the bias point $Q$ . At $Q$ the slope of the tangent line (pink) is $g_{m} = I_{C} / V_{T}$ . Notice the tangent is much steeper than the dashed line drawn from the origin — that dashed line's slope is $I_{C} / V_{B E}$ , the wrong ratio people reach for. The gap between them is exactly the factor $V_{B E} / V_{T} \approx 0.7/0.0259 \approx 27$ .

Cell A — BJT, plain

Cell B — BJT, temperature dependence

Worked example Example 2 — same BJT, hot day (cell B)

The same $I_{C} = 0.5 mA$ transistor now runs at $T = 350 K$ instead of $300 K$ . Recall $V_{T} = k T / q$ , so $V_{T}$ scales linearly with absolute temperature. Find the new $g_{m}$ .

Forecast: hotter → bigger $V_{T}$ → smaller $g_{m}$ . Guess it drops a bit below $19.3$ mS.

Scale $V_{T}$ with temperature: $V_{T} (350) = 25.9 mV \times \frac{350}{300} = 30.2 mV$ . Why this step? $V_{T} = k T / q$ is proportional to $T$ (in kelvin). See Thermal Voltage VT. Only $T$ changed, so ratio it up.
Recompute: $g_{m} = \frac{0.5 \times 1 0 ^{- 3}}{30.2 \times 1 0 ^{- 3}} = 16.6 mS$ . Why this step? Same $g_{m} = I_{C} / V_{T}$ ; only the denominator moved.

Verify: $g_{m}$ fell from $19.3$ to $16.6$ mS — the ratio is $\frac{300}{350} = 0.857$ , exactly $\frac{16.6}{19.3}$ ✔. Hotter transistor is a weaker transconductor at the same current. Forecast confirmed. ✔

Cell C — MOSFET from the overdrive

Cell D — MOSFET from the drain current only

Worked example Example 4 — MOSFET, only

$I_{D}$ and $k$ known (cell D) A MOSFET has $k = 4 mA/V^{2}$ and sits at $I_{D} = 2 mA$ . You are not told $V_{o v}$ . Find $g_{m}$ .

Forecast: $2 k I_{D}$ has a square root, so $g_{m}$ won't scale linearly — expect a "compressed" number, several mS.

Pick the form that uses the knowns: $g_{m} = 2 k I_{D}$ . Why this step? Of the three MOSFET forms, only this one avoids needing $V_{o v}$ . See MOSFET Square-Law and Saturation.
Plug in with consistent units (amps and A/V²): $k = 4 \times 1 0^{- 3}$ , $I_{D} = 2 \times 1 0^{- 3}$ , so $g_{m} = 2 (4 \times 1 0^{- 3}) (2 \times 1 0^{- 3}) = 1.6 \times 1 0^{- 5} = 4.0 \times 1 0^{- 3} S = 4 mS$ . Why this step? $2 \cdot 4 \cdot 2 = 16$ , and $1 0^{- 3} \cdot 1 0^{- 3} = 1 0^{- 6}$ , giving $16 \times 1 0^{- 6} = 1.6 \times 1 0^{- 5}$ ; its root is $4 \times 1 0^{- 3}$ .

Verify: Recover $V_{o v}$ : from $g_{m} = k V_{o v}$ , $V_{o v} = g_{m} / k = \frac{4 mS}{4 mA/V ^{2}} = 1 V$ . Then check $I_{D} = \frac{k}{2} V_{o v}^{2} = \frac{4}{2} (1)^{2} = 2 mA$ ✔ — matches the given bias.

Cell E — same current, BJT vs FET

Worked example Example 5 — fair fight at 2 mA (cell E)

Bias both a BJT and a MOSFET at $I = 2 mA$ . The MOSFET runs at $V_{o v} = 0.25 V$ , $V_{T} = 25.9 mV$ . Which has more $g_{m}$ , and by what factor?

Forecast: the parent note says BJTs win per amp — expect the BJT to be several times larger.

BJT: $g_{m, BJT} = \frac{I _{C}}{V _{T}} = \frac{2 \times 1 0 ^{- 3}}{25.9 \times 1 0 ^{- 3}} = 77.2 mS$ . Why this step? Cell A machinery, larger current.
MOSFET: $g_{m, FET} = \frac{2 I _{D}}{V _{o v}} = \frac{2 ( 2 mA )}{0.25 V} = 16 mS$ . Why this step? We know $I_{D}$ and $V_{o v}$ , so the $2 I_{D} / V_{o v}$ form is fastest.
Ratio: $\frac{77.2}{16} = 4.83$ . Why this step? The whole point is the efficiency gap at equal current.

Verify: The ratio equals $\frac{I / V _{T}}{2 I / V _{o v}} = \frac{V _{o v}}{2 V _{T}} = \frac{0.25}{2 ( 0.0259 )} = 4.83$ ✔ — independent of the current value, as it must be. The BJT gives ~ $4.8 \times$ more transconductance per amp here.

Cell F — fixed $I_{D}$ , sweep $V_{o v}$ (the counter-intuitive one)

Figure 2.

Figure 2 keeps the two pictures separate on purpose — read it as two different questions, not one device doing two things.

Question 1 (pink curve, "one device, turn up the gate"): take a single fixed device (fixed $k$ ) and raise its overdrive. Its current $I_{D} = \frac{k}{2} V_{o v}^{2}$ rises, and $g_{m} = k V_{o v}$ rises straight-line with $V_{o v}$ . This is what happens when you crank the gate drive of one transistor.
Question 2 (blue curve, "hold the current, pick the right device"): insist the drain current stays pinned at $I_{D} = 1 mA$ . Then $g_{m} = 2 I_{D} / V_{o v}$ falls as $V_{o v}$ grows. But you cannot slide along this blue curve with one fixed transistor — each point on it corresponds to a different device whose $W / L$ (hence $k$ ) is chosen so that this fixed current is reached at that overdrive. The blue curve is a design locus across devices, not a bias sweep of one device.

Keeping these apart is the whole lesson: "more overdrive" helps $g_{m}$ only if you let the current rise (pink). At fixed current (blue), more overdrive costs you $g_{m}$ .

Worked example Example 6 — hold

$I_{D}$ , double the overdrive (cell F) You want a MOSFET operating at $I_{D} = 1 mA$ . Compare two candidate designs: one at $V_{o v} = 0.2 V$ and one at $V_{o v} = 0.4 V$ . Which delivers more $g_{m}$ ?

Forecast: naive instinct says "more overdrive → more $g_{m}$ ." But we are pinning current...

Candidate A, $V_{o v} = 0.2 V$ at $I_{D} = 1 mA$ : $g_{m} = \frac{2 I _{D}}{V _{o v}} = \frac{2 ( 1 mA )}{0.2 V} = 10 mS$ . Why this step? Fixed $I_{D}$ forces the $2 I_{D} / V_{o v}$ form — it's the one that holds current constant while overdrive varies.
Candidate B, $V_{o v} = 0.4 V$ at $I_{D} = 1 mA$ : $g_{m} = \frac{2 ( 1 mA )}{0.4 V} = 5 mS$ . Why this step? Same current, larger denominator → smaller $g_{m}$ .
These are two different transistors. Candidate A needs $k_{A} = \frac{2 I _{D}}{V _{o v}^{2}} = \frac{2 ( 1 mA )}{( 0.2 ) ^{2}} = 50 mA/V^{2}$ (a wide device); Candidate B needs $k_{B} = \frac{2 ( 1 mA )}{( 0.4 ) ^{2}} = 12.5 mA/V^{2}$ (a narrower one). Why this step? This is the blue-curve/across-devices picture from Figure 2 made concrete — each fixed-current point demands its own $W / L$ . It resolves the confusion: we are not raising the gate of one transistor.

Verify: Cross-check each with $g_{m} = k V_{o v}$ : A gives $50 mA/V^{2} \times 0.2 V = 10 mS$ ✔; B gives $12.5 mA/V^{2} \times 0.4 V = 5 mS$ ✔. The forecast's naive instinct was wrong — at fixed current, the low-overdrive (wider) device wins on $g_{m}$ . Tradeoff: it costs more silicon area and gives less voltage headroom.

Cell G — degenerate, zero, subthreshold, and PFET inputs

Worked example Example 7 — the limits, weak inversion, and the sign of

$g_{m}$ (cell G) Evaluate $g_{m}$ in five situations and say what physically happens.

(a) BJT as $I_{C} \to 0$ .

$g_{m} = I_{C} / V_{T} \to 0$ as $I_{C} \to 0$ . Why this step? The exponential curve near the origin is almost flat, so a voltage wiggle moves almost no current.
Physical reading: a transistor with no bias current has no gain. This is why you must bias a stage into its active region before it amplifies.

(b) MOSFET at threshold in strong inversion, $V_{o v} \to 0^{+}$ (i.e. $V_{GS} = V_{t h}$ ).

From the square-law form $g_{m} = k V_{o v}$ : $g_{m} \to 0$ as $V_{o v} \to 0$ . Why this step? At exactly threshold the square-law channel just barely exists; square-law $I_{D} \to 0$ too.
Watch the trap: the form $g_{m} = 2 I_{D} / V_{o v}$ looks like $0/0$ here. It is not a real singularity — both numerator and denominator vanish. Using $k V_{o v}$ or $2 k I_{D}$ resolves it cleanly to $0$ . Why this step? Always pick the non-degenerate form near a limit. $2 k I_{D} \to 0 = 0$ unambiguously.

(c) MOSFET below threshold — the subthreshold (weak-inversion) regime.

The ideal square law says $I_{D} = 0$ for $V_{GS} < V_{t h}$ , so the square-law $g_{m}$ is $0$ . But real MOSFETs conduct a small exponential current below threshold: $I_{D} \approx I_{S 0} e^{V_{GS} / (n V_{T})}$ , where $n \approx 1.3 - 1.5$ is the subthreshold slope factor. Why this step? Below threshold the channel is not fully formed; conduction is by diffusion, which is exponential in $V_{GS}$ — mathematically just like a BJT.
Differentiate that exponential exactly as we did for the BJT: $g_{m} = \frac{d I _{D}}{d V _{GS}} = \frac{I _{D}}{n V _{T}}$ . So the subthreshold $g_{m}$ is not zero — it is the BJT-like result, only weakened by the factor $n$ . Why this step? The derivative of $e^{V_{GS} / (n V_{T})}$ brings down $1/ (n V_{T})$ and the exponential re-becomes $I_{D}$ — identical algebra to $g_{m} = I_{C} / V_{T}$ .
Numeric taste: a MOSFET leaking $I_{D} = 10 μ A$ in weak inversion with $n = 1.4$ , $V_{T} = 25.9 mV$ has $g_{m} = \frac{10 \times 1 0 ^{- 6}}{1.4 \times 25.9 \times 1 0 ^{- 3}} = 0.276 mS$ . Why this step? Shows the leakage- $g_{m}$ is small but genuinely nonzero — important for ultra-low-power design.

(d) PFET (p-channel MOSFET) — the sign of $g_{m}$ .

In a PFET the drain current increases in magnitude as $V_{GS}$ goes more negative (the overdrive is $V_{o v} = V_{S G} - ∣ V_{t h} ∣ > 0$ , with $V_{GS} = - V_{S G} < 0$ ). If we keep the same NMOS sign convention ( $I_{D}$ flowing into the drain, $V_{GS}$ from gate to source), then raising $V_{GS}$ (making it less negative) reduces the PFET current, so $g_{m} = \partial I_{D} / \partial V_{GS}$ is negative. Why this step? The physics is mirror-imaged: holes instead of electrons, and the controlling voltage runs the other way.
The clean fix designers use: define PFET quantities in magnitudes — $∣ g_{m} ∣ = k_{p} ∣ V_{o v} ∣ = 2 I_{D} /∣ V_{o v} ∣ = 2 k_{p} I_{D}$ , identical in form to the NMOS. So the size of the transconductance obeys the exact same three formulas; only the raw sign flips with the convention. Why this step? Keeps every worked formula on this page usable for PFETs — just track magnitudes and remember the phase.

Verify: Limits (a) and (b) give $g_{m} = 0$ (no controllable current ⇒ no transconductance) ✔. Case (c) gives a finite $g_{m} = I_{D} / (n V_{T}) = 0.276 mS$ — smaller than a BJT at the same current by exactly the factor $n = 1.4$ , since $\frac{I _{D} / ( n V _{T} )}{I _{D} / V _{T}} = 1/ n$ ✔. Case (d): with a PFET at $∣ V_{o v} ∣ = 0.25 V$ , $I_{D} = 1 mA$ , $∣ g_{m} ∣ = 2 (1 mA) /0.25 V = 8 mS$ — same magnitude formula as NMOS ✔. Units: $\frac{A}{V} = S$ throughout ✔.

Cell H — real-world word problem (design backwards)

Worked example Example 8 — "I need a gain of −100" (cell H)

You must design a common-source stage (Common-Source Amplifier) with voltage gain $A_{v} = - 100$ using a load $R_{L} = 10 k Ω$ . The MOSFET has $k = 5 mA/V^{2}$ . Find the required $g_{m}$ , the bias current $I_{D}$ , and the overdrive $V_{o v}$ .

Forecast: gain $= g_{m} R_{L}$ , and $R_{L} = 10 k$ , so $g_{m}$ must be about $10 mS$ .

From $A_{v} = - g_{m} R_{L}$ , solve for $g_{m}$ : $g_{m} = \frac{∣ A _{v} ∣}{R _{L}} = \frac{100}{10 \times 1 0 ^{3}} = 10 \times 1 0^{- 3} S = 10 mS$ . Why the minus sign in $A_{v} = - g_{m} R_{L}$ ? In a common-source stage the small-signal drain current is $i_{d} = g_{m} v_{g s}$ . That current flows out of the supply, down through $R_{L}$ , into the drain, so a rise in input voltage pulls more current through $R_{L}$ , dropping more voltage across it and pulling the output node down. Input up → output down is a $18 0^{\circ}$ phase inversion, which is exactly what the negative sign records. We take the magnitude here because we only need the required $g_{m}$ .
Get $V_{o v}$ from $g_{m} = k V_{o v}$ : $V_{o v} = \frac{g _{m}}{k} = \frac{10 mS}{5 mA/V ^{2}} = 2 V$ . Why this step? We know $g_{m}$ and $k$ ; this form gives the overdrive directly. (Note $10 mS = 10 mA/V$ , so dividing by $k$ in $mA/V^{2}$ leaves volts — units are consistent.)
Get the bias current from the square law: $I_{D} = \frac{k}{2} V_{o v}^{2} = \frac{5}{2} (2)^{2} = 10 mA$ . Why this step? Now that $V_{o v}$ is fixed, the current follows.

Verify: Full loop — $g_{m} = 2 I_{D} / V_{o v} = 2 (10 mA) /2 V = 10 mS$ ✔, and $A_{v} = - g_{m} R_{L} = - (10 mS) (10 k Ω) = - (10 \times 1 0^{- 3} S) (10 \times 1 0^{3} Ω) = - 100$ ✔. Sanity note: $I_{D} = 10$ mA and $V_{o v} = 2$ V is a thirsty, high-headroom design — a real engineer would cut $R_{L}$ or use a current-source load, but the arithmetic closes exactly.

Cell I — exam-style twist

Worked example Example 9 — the ratio trap plus a scaling question (cell I)

A student computes a BJT's $g_{m}$ as $I_{C} / V_{B E}$ with $I_{C} = 1 mA$ , $V_{B E} = 0.7 V$ , getting $1.43 mS$ . (i) What is the correct $g_{m}$ ? (ii) By what factor did they err? (iii) If you then triple the collector current, what happens to the correct $g_{m}$ ?

Forecast: the ratio grossly undercounts (parent note said ~27×), and tripling $I_{C}$ triples $g_{m}$ (BJT is linear).

Correct $g_{m}$ : use the derivative result $g_{m} = I_{C} / V_{T} = \frac{1 mA}{25.9 mV} = 38.6 mS$ . Why this step? $g_{m}$ is a slope, not a DC ratio — the exponential's derivative brings the $1/ V_{T}$ . See Figure 1.
Error factor: $\frac{g _{m, correct}}{g _{m, wrong}} = \frac{38.6}{1.43} = 27.0$ . Why this step? This ratio equals $\frac{I _{C} / V _{T}}{I _{C} / V _{B E}} = \frac{V _{B E}}{V _{T}} = \frac{0.7}{0.0259} = 27.0$ — the whole discrepancy is $V_{B E} / V_{T}$ , the same "27" from Figure 1.
Triple the current: BJT $g_{m} \propto I_{C}$ , so $g_{m} \to 3 \times 38.6 = 115.8 mS$ . Why this step? Linear scaling — contrast with a MOSFET, where tripling $I_{D}$ multiplies $g_{m}$ by only $3 = 1.73$ . See BJT Small-Signal Model.

Verify: (i) $1 mA /25.9 mV = 38.6 mS$ ✔. (ii) $V_{B E} / V_{T} = 0.7/0.0259 = 27.03$ , matching $38.6/1.43$ ✔. (iii) $3 \times 38.6 = 115.8 mS$ ; directly $3 mA /25.9 mV = 115.8 mS$ ✔.

Active recall

Recall Which formula do I reach for? (hide answers)

Given only $I_{C}$ (BJT)? ::: $g_{m} = I_{C} / V_{T}$ .
Given $k$ and $V_{o v}$ ? ::: $g_{m} = k V_{o v}$ .
Given $I_{D}$ and $V_{o v}$ (fixed current)? ::: $g_{m} = 2 I_{D} / V_{o v}$ .
Given $I_{D}$ and $k$ only (no $V_{o v}$ )? ::: $g_{m} = 2 k I_{D}$ .
Subthreshold (weak inversion) MOSFET? ::: $g_{m} = I_{D} / (n V_{T})$ — BJT-like, weakened by $n$ .
PFET? ::: same magnitude formulas; sign of $g_{m}$ flips with the NMOS convention — track $∣ g_{m} ∣$ .
Near a $0/0$ limit at threshold? ::: use $k V_{o v}$ or $2 k I_{D}$ , never $2 I_{D} / V_{o v}$ .

Recall Scaling reflexes

Triple $I_{C}$ (BJT) → $g_{m}$ does what? ::: triples (linear).
Triple $I_{D}$ (MOSFET, strong inversion) → $g_{m}$ does what? ::: $\times 3 \approx 1.73$ .
Raise $T$ at fixed $I_{C}$ → $g_{m}$ ? ::: falls (since $V_{T} \propto T$ ).
Raise $V_{o v}$ at fixed $I_{D}$ → $g_{m}$ ? ::: falls (halving overdrive doubles $g_{m}$ ).

Connections

Transconductance (gm) — the parent; this page drills its formulas across every case.
Thermal Voltage VT — Ex 2's temperature scaling of $V_{T} = k T / q$ ; also the $n V_{T}$ of subthreshold.
MOSFET Square-Law and Saturation — source of the three FET forms used in Ex 3–8.
Overdrive Voltage Vov — the $g_{m}$ /current tradeoff of Ex 6.
Common-Source Amplifier — the backwards design of Ex 8 and the phase-inversion sign.
Common-Emitter Amplifier — BJT dual of the same gain link.
BJT Small-Signal Model — the linear $g_{m} \propto I_{C}$ scaling of Ex 9.
Early Effect and Output Resistance ro — pairs with $g_{m}$ for intrinsic gain (a next drill).