5.6.13 · D1Machine Learning (Aerospace Applications)

Foundations — LSTM — gates, cell state

2,743 words12 min readBack to topic

This page assumes nothing. Before you can read the parent note LSTM — gates, cell state, you need to recognise a handful of symbols on sight. We build each one from a picture, in an order where every symbol only uses ones already defined.


0. What a "vector" and a "timestep" mean

Before any equation, two ideas the parent note silently assumes.

Figure — LSTM — gates, cell state

Look at the figure: the grid shows three rows (labelled "ch 1", "ch 2", "ch 3" on the vertical axis) and four columns (labelled to on the horizontal axis). The orange box frames a single column — that column is one input vector . Reading down a column gives you all channels at one instant; reading across a row shows one channel evolving over time.

Recall Why sequences at all?

Because aerospace data — vibration, temperature, RPM — arrives as a stream over time, and the order carries meaning. See Time Series Forecasting.


1. The input symbol and the two memories ,

Now we can name the three vectors that flow through the machine.

Why two memories? A plain RNN keeps only one note () and rewrites it every tick, smearing out old information. The LSTM adds as a "conveyor belt" that can carry a message for thousands of ticks without being overwritten. That extra line is the entire reason LSTMs beat RNNs.

Figure — LSTM — gates, cell state

Look at the figure: the horizontal axis is the timestep . The thick blue line near the top is the cell state — notice it stays almost flat, and the pale blue arrows between ticks show information sliding forward with little change (a "highway"). The thin gray line along the bottom is the hidden state — it jumps up and down every tick because it is rewritten each time. The flatness of the blue line is exactly what "protected memory" looks like.


2. The bracket — concatenation, and the name

Why concatenate? Each gate needs to look at both what the machine remembers () and what just arrived () to make its decision. Gluing them together into lets a single weight layer see everything at once.


3. Weight matrix , bias , and the "affine map"

Why do we need it? The gates must be learnable. The numbers in and are exactly what training adjusts so the machine discovers, on its own, when to remember and when to forget.


4. The squashers: (sigmoid) and

Affine maps can output any number, huge or tiny. We need to squash them into a controlled range. Two squashers appear. Both first need one constant.

Figure — LSTM — gates, cell state

Look at the figure: the horizontal axis is the raw input value (the number coming out of ); the vertical axis is the squashed output. The blue curve is — it hugs the dotted line at on the right and on the left, and the blue dot marks . The orange curve is — it saturates at the dotted lines and , and the orange dot marks , i.e. it passes through the origin. Both are flat (saturated) at the ends and steep in the middle.

Why sigmoid for a gate? A number in is a perfect valve-opening fraction: = fully shut (block everything), = fully open (pass everything), = half open. Why tanh for the candidate note? Because a new memory value might need to be positive or negative; allows signed, zero-centred writes. More on both in Sigmoid and Tanh Activations.


5. The elementwise product

Why elementwise and not matrix multiply? A gate decides, per channel, how much to let through. Channel 5's valve should touch only channel 5's memory — no mixing. That independence is exactly what gives.

Figure — LSTM — gates, cell state

Look at the figure: the horizontal axis lists four channels (ch1–ch4); the vertical axis is value. For each channel there are three bars — gray is the memory value before gating, blue is the gate value (printed above each bar, all in to ), and green is the result . The red arrow points at ch3, where the gate is : its green result bar vanishes — that channel is blacked out. Where the gate is (ch1) the green bar equals the gray bar exactly; where it is the green bar is halved.


6. Naming the four gate outputs

Now every ingredient is defined — , , , , , elementwise application — so the parent's four names finally make sense, with their affine arguments spelled out in full.

The whole update, in words you can now decode:

Recall Why the additive "+" is the hero

Because is built by adding to (not overwriting), the memory can survive many steps — this is what defeats the vanishing gradient problem, and what the GRU achieves more cheaply.


Prerequisite map

Vector = list of numbers

Timestep t subscript

Inputs x_t and states h_t c_t

Concatenation z_t = h_prev with x_t

Affine map W times z plus b

Sigmoid squasher 0 to 1

Tanh squasher minus1 to 1

Gate = valve fraction

Elementwise product gate times memory

Candidate signed new note

Cell update keep plus add

LSTM gates and cell state


Equipment checklist

Read a term inside :::; say it aloud first, then reveal to check yourself.

A "vector" is
an ordered list of numbers, one slot per channel (e.g. per sensor); its "size" is the slot count.
The subscript in means
the value at timestep (clock tick) ; is one tick earlier.
versus
= short-term memory and output; = protected long-term memory (the conveyor belt).
The initial states and are
usually all-zero vectors — a blank note and empty memory used at the first tick.
means
concatenation — glue the two lists into one longer list (size ) so a gate sees both memory and input.
is
an affine map — a learnable weighted mix () plus a constant shift ().
Shape of and for an output of size from input of size
is and is size — rows = output size, columns = input size.
and are
the candidate gate's own weight matrix and bias, used in .
Euler's number is
a fixed constant ; , and it is the natural base of the squasher curves.
outputs values in
the open interval — perfect as a valve-opening fraction.
outputs values in
the open interval , centred at — allows signed candidate values.
"Applied elementwise" means
run the squasher separately on each slot of the vector; size- in, size- out, no slot affects another.
means
elementwise product — multiply slot by slot, no channel mixing.
A "gate" is made from
a sigmoid (to get a fraction) applied via to a memory vector.
Why wraps in
is a running additive sum that can grow unbounded; squashes it to so the output stays stable.
The tilde in signals
a proposed candidate memory, not yet committed to the cell.

Connections