SpaceWire — high-speed serial link standard for spacecraft: Visual walkthrough

5.5.27 · D2 · Coding › Embedded Systems & Real-Time Software › SpaceWire — high-speed serial link standard for spacecraft

Yeh page SpaceWire ka visual companion hai. Agar koi term yahan rushed lage, toh uska ghar parent note hai.

Step 1 — "Bit bhejna" ka matlab kya hota hai

KYA. Do chips ke beech ek wire sirf ek piece of metal hai jise hum do voltages mein se kisi ek par rakhhte hain: ek high voltage (ise 1 kaho) ya ek low voltage (ise 0 kaho). Message 1 0 1 1 bhejna ke liye sender time ko equal slots mein kaatata hai — ek slot per bit — aur har slot mein wire ko matching level par set karta hai. Ek slot bhar ki time ko bit period kehte hain, likha jaata hai $T$ .

KYUN. "Timing recover karna" ki baat karne se pehle hume agree karna hoga ki timing hoti kya hai: yeh jaanna ki har bit period $T$ kahan shuru aur kahan khatam hoti hai. Agar receiver in boundaries ko galat judge kare, toh woh galat slot padhega aur message garbage ho jaayega.

PICTURE. Figure s01 mein chaar bit slots gray columns ki tarah hain, har ek ki width $T$ hai, aur Data line 1 0 1 1 spell karne ke liye high aur low ke beech step karti hai.

Figure — SpaceWire — high-speed serial link standard for spacecraft

Step 2 — Naive idea: alag clock wire bhejna, aur yeh kyun fail hota hai

KYA. "Har slot kahan shuru hota hai?" ka obvious fix yeh hai ki ek doosra wire add karo — ek clock — jo har bit par ek baar upar-neeche tick kare. Receiver Data wire ko tab read karta hai jab bhi clock tick kare. Yahi ek simple parallel bus kaam karta hai.

KYUN (yeh crux hai). Ek spacecraft mein do wires metres tak side by side chalti hain, temperature swings aur radiation se guzar kar. Yeh thodi alag rates par stretch aur age hoti hain. Toh clock ki tick aur data ki slot boundary धीरे-धीरे alag ho jaati hain. Is sliding gap ko skew kehte hain. Jab skew half a bit period se zyada ho jaata hai, receiver galat slot sample karta hai. Ek shared clock ek single fragile reference hai jis par environment seedha attack karta hai.

PICTURE. Figure s02 mein Data aur alag Clock left par aligned hain, phir Clock rightward drift karte hue dikhaya gaya hai (orange arrow) jab tak uski tick galat Data slot ke andar nahi land kar jaati — red "wrong sample" marker.

Lesson yeh hai: hume timing ko unhi wires ke andar rakhna hoga jो data carry karti hain, taaki jo bhi ek ko stretch kare woh doosre ko exactly same tarah stretch kare.

Step 3 — Woh ek rule jo hume bachata hai: har slot mein exactly ek edge guarantee karo

KYA. Ek edge woh moment hai jab ek wire apna level switch karti hai (low→high ya high→low). Yahan design goal hai, seedha likha gaya: ensure karo ki har bit period mein exactly ek edge kahin na kahin hoti hai. Agar yeh sach hai, toh receiver sirf edges count karta hai — ek edge, ek naya bit — aur usse kabhi external clock ki zaroorat nahi padti.

KYUN. Dekho ki akela Data wire identical bits ke run par kya karta hai, jaise 1 1 1. Uska level hai high, high, high — flat, koi edge nahi. Us flat run ke dauran receiver ko yeh batane ka koi tarika nahi ki teen slots hain ya ek lamba slot. Toh Data akela "ek edge per slot" guarantee nahi kar sakta. Hume ek helper chahiye jo edge produce kare exactly jab Data flat ho.

PICTURE. Figure s03 mein pattern 1 1 0 0 1 dikhaya gaya hai. Top row (Data) do 1s mein flat hai aur do 0s mein flat hai — red boxes un "silent" slots ko mark karti hain jahan Data koi edge nahi deta. Precisely yahi woh silent slots hain jahan ek helper ko kaam karna chahiye.

Step 4 — Strobe wire aur uska toggle rule

KYA. Ek doosra wire add karo jiska naam hai Strobe, likha jaata hai $S$ . Uska rule sirf ek line ka hai:

Strobe us slot mein toggle karta hai agar aur sirf agar Data pichle bit se nahi badla.

Words mein symbols ke saath, $b_{n}$ ko bit number $n$ ki value maan ke:

$S (n) = S (n - 1) \oplus \overline{(b_{n} \oplus b_{n - 1})}$

Har symbol ko wahan se padho jahan woh baitha hai:

$b_{n} \oplus b_{n - 1}$ — symbol $\oplus$ XOR hai, jo 1 output karta hai jab uske do inputs differ karein. Toh yeh poora bracket exactly tab 1 hai jab bit changed (Data ne already ek edge bana li).
$\overline{(\dots)}$ — overbar NOT hai, value flip karta hai. Toh $\overline{b_{n} \oplus b_{n - 1}}$ exactly tab 1 hai jab bit same rahi (Data silent tha).
$S (n - 1) \oplus (\dots)$ — pichle Strobe ko 1 se XOR karna use flip karta hai (ek toggle); 0 se XOR karna use unchanged rehne deta hai.

Mila ke: agar Data is slot mein silent tha, Strobe flip karo; warna Strobe waise hi chhoddo. Exactly wahi helper jo Step 3 ne maanga tha.

XOR aur NOT kyun, koi aur operation kyun nahi? Hume ek "kya bit change hui?" detector chahiye tha — yeh literally XOR ki definition hai (differ → 1). Hume "uska ulta" chahiye tha — yeh NOT hai. Aur hume "wire ko command par flip karna" chahiye tha — yeh XOR-with-1 hai (ek controlled toggle). Har tool ek precise sub-question ka jawab deta hai; kuch bhi fancy required nahi hai.

PICTURE. Figure s04 mein 1 1 0 1 0 0 ke liye Data aur Strobe saath mein draw hain. Ek green tick har us slot ke neeche hai jahan Strobe toggle karta hai (repeated-bit slots); ek blue tick har us slot ke neeche hai jahan Data toggle karta hai. Notice karo ki ticks kabhi overlap nahi karte aur kabhi dono ek saath missing nahi hote.

Step 5 — Promise prove karo: har slot mein exactly ek edge, hamesha

KYA. Ab hum har possible slot check karte hain aur confirm karte hain ki "exactly ek edge" ka promise kabhi fail nahi ho sakta.

KYUN. Ek rule jise tum kisi bhi case mein break nahi kar sakte, trust karne laayak hai; ek rule jo "usually" kaam karta hai woh ek baar slip hone par data corrupt karta hai. Toh hum enumerate karte hain — sirf do cases hain.

Case A — bit change hui ( $b_{n} \neq = b_{n - 1}$ ): Data toggles (Data par ek edge). Bracket $\overline{b_{n} \oplus b_{n - 1}}$ 0 hai, toh Strobe flat rehta hai. Result: exactly ek edge, Data par.

Case B — bit same rahi ( $b_{n} = b_{n - 1}$ ): Data flat rehta hai. Bracket 1 hai, toh Strobe toggles. Result: exactly ek edge, Strobe par.

Koi teesra case nahi hai — do bits ya toh match karenge ya differ karenge. Toh har slot mein exactly ek edge hoti hai, ya toh Data par ya Strobe par. Timing ab hamesha ke liye sirf do wires se recover ki ja sakti hai.

PICTURE. Figure s05 ek do-cell truth table hai picture ki tarah: left cell "bit changed → Data edge, Strobe flat", right cell "bit same → Strobe edge, Data flat", dono mein ek mini-waveform hai. Ek bada check-mark dono par span karta hai: "one edge per slot".

Step 6 — Receiver clock rebuild karta hai: do edge streams ko XOR karo

KYA. Receiver kisi bhi wire par edges dekhta hai. "Kya Data change hua?" OR "Kya Strobe change hua?" combine karne par ek slot per tick milta hai — woh reconstructed tick train hi recovered clock hai. Formally receiver yeh form karta hai:

$RecoveredClock (n) = Data (n) \oplus Strobe (n)$

Term by term:

$Data (n)$ — Data wire ka current level.
$Strobe (n)$ — Strobe wire ka current level.
$\oplus$ — phir se XOR: kyunki exactly ek ne is slot mein flip kiya, is XOR ki value ek baar per slot flip hoti hai. Ek signal jo ek baar per slot flip hota hai woh hi ek clock hai jo ek baar per slot tick karta hai.

Phir receiver har clock edge par Data wire ko sample karta hai $b_{n}$ directly padhne ke liye. Data kabhi encoded nahi hua — yeh seedha apni wire se padha jaata hai, self-made clock se time karke.

KYUN. Kyunki clock aur data ab same twisted pairs par sawaari karte hain, koi bhi stretch ya radiation-slowing dono ko identically hit karta hai — Step 2 ka skew khul nahi sakta. Reference signal ke andar rehta hai.

PICTURE. Figure s06 mein 1 0 0 1 1 ke liye chaar rows stack hain: Data, Strobe, phir recovered clock (Data XOR Strobe) har slot mein ek clean tick ke saath, phir blue sampling arrows Data par har tick par girte hain aur 1 0 0 1 1 read karte hain.

Step 7 — Degenerate case: ek all-same run ("flat forever" test)

KYA. Design ko uski worst input par push karo: identical bits ka ek lamba run, 1 1 1 1 1. Yahi woh case hai jisne Step 3 mein akele-Data idea ko maar diya tha.

KYUN. Agar encoding apni sabse nasty input survive kar le, toh woh sab kuch survive kar leti hai. All-same sabse nasty hai kyunki Data poore time perfectly flat rehta hai — Data par har slot "silent" hai.

Step 4 ka rule chalate hain: har bit apne predecessor se match karti hai, toh har slot Strobe toggle karta hai. Strobe ek steady square wave ban jaata hai jo ek baar per slot tick karta hai. Flat Data ko toggling Strobe ke saath XOR karne par ek clean recovered clock milta hai. Exactly woh case jo naive scheme ko todta tha, wahi case hai jise DS sabse cleanly handle karta hai.

Mirror degenerate case — alternating bits 1 0 1 0 1 — Data ko har slot toggle karta hai aur Strobe ko flat rakhta hai; same guarantee, roles swap hoke. In do extremes ke beech, har real pattern sirf ek mix hai, aur Step 5 ne already har slot cover kar li.

PICTURE. Figure s07 mein do extremes side by side hain: left, all-1s ke saath flat Data aur toggling Strobe; right, alternating bits ke saath toggling Data aur flat Strobe. Dono ke neeche same tidy recovered clock milti hai.

Ek-picture summary

Figure s08 poori journey compress karta hai: upar bit stream; neeche Data aur Strobe toggle rule follow karte hue (green = Strobe fired, blue = Data fired, exactly ek per slot); recovered clock unka XOR hai; aur blue sampling arrows original bits wapas read karte hain — ek aisi cable par jahan ek crossed-out clock wire yaad dilaati hai ki koi zaroorat nahi thi.

Recall Feynman retelling — simple words mein bol ke dikhao

Do chips do metal wires share karti hain. Ek wire, Data, sirf har bit ki value hold karti hai — 1 ke liye high, 0 ke liye low. Problem: agar tum same bit do baar bhejo, Data hilti nahi, aur receiver ka slot count khatam ho jaata hai. Purane buses ne ek teesri clock wire se fix kiya, lekin space mein woh wire step se drift ho jaati hai (skew) aur poori cheez corrupt ho jaati hai.

SpaceWire ka fix: ek doosri wire, Strobe, ek rule ke saath — jab Data nahi hile tab khud hilo. Ab, har single bit slot mein, exactly ek wire hilti hai. Receiver ko bilkul clock ki zaroorat nahi: woh bas notice karta hai "do wires mein se ek abhi hili → naya bit → abhi Data padho." Mathematically "do mein se ek hili" Data XOR Strobe hai, jo ek baar per slot flip karta hai — yahi flipping hi clock hai, signal se free mein bana liya. Kyunki clock ab data ke saath same wires par rehti hai, kuch bhi drift apart nahi ho sakta. Yahan tak ki worst input — same bit hamesha ke liye — perfectly handle hoti hai: Strobe bas har slot tick karta hai. Bas yahi poori idea hai.

Recall Quick self-check

Space mein alag clock wire kyun fail hoti hai? ::: Clock aur data independently routed hain, toh temperature/radiation unhe drift apart karte hain (skew) jab tak clock tick galat data slot mein nahi land kar jaati. Strobe wire kya karta hai? ::: Yeh exactly tab toggle karta hai jab Data nahi karta, do wires mein har bit period mein exactly ek edge guarantee karta hai. Receiver clock kaise recover karta hai? ::: Data aur Strobe ko XOR karke — kyunki exactly ek per slot flip karta hai, XOR ek baar per slot flip karta hai, har bit mein ek tick deta hai; woh har tick par Data sample karta hai. Kya bit value Data XOR Strobe hai? ::: Nahi — bit value sirf Data line hai; XOR clock rebuild karta hai, data nahi.

Related: LVDS Signaling (woh physical wires jo Data aur Strobe carry karti hain), Cosmic Ray Effects on Electronics (kyun skew aur single-bit glitches matter karte hain), Serial vs Parallel Communication (kyun yahan do wires wide parallel bus se behtar hain).