Real-time constraints — hard and soft deadlines

5.5.12 · Coding › Embedded Systems & Real-Time Software

Real-time system KYA hota hai?

Key quantity hai deadline: woh latest time jis tak task ka response complete hona chahiye, task ke release (arrival) time se measure karke.

Deadlines classify kyun karein? Hard vs Soft vs Firm

Miss hua deadline ki cost application se application bahut alag hoti hai. Hum classify karte hain utility ke basis pe — ek result jo apni deadline ke baad deliver ho, uski utility kya hai.

Figure — Real-time constraints — hard and soft deadlines

Hard deadline KAISE guarantee karein?

Aap "test karte raho jab tak fast laage" wali approach nahi le sakte. Hard real-time ko ek provable bound chahiye. Recipe yeh hai:

Har task ke liye WCET $C_{i}$ determine karo (static analysis ya measured worst case).
Ek scheduling policy chuno (e.g. fixed-priority Rate-Monotonic, ya EDF).
Ek schedulability test chalao: ek mathematical proof ki worst-case load mein sabhi deadlines meet hongi.

Sabse simple test derive karna: CPU utilisation bound

Soft deadlines: ek alag goal

Soft real-time ke liye aap zero misses prove nahi karte — aap statistics bound karte ho: jaise "99.9% frames 16 ms mein render honge," ya average tardiness $max (0, R_{i} - D_{i})$ minimize karo. Design knob hai graceful degradation: crash karne ki jagah quality drop karo, frames skip karo, ya load shed karo.

Flashcards

Ek system ko "real-time" kya banata hai?

Correctness dono pe depend karta hai — logical result aur woh time jab woh produce hota hai (timeliness correctness ka hissa hai).

Hard deadline — miss hone ka consequence?

Catastrophic / total system failure; late result invalid hai.

Firm deadline — miss hone ka consequence?

Late result ki zero value hoti hai aur discard ho jaata hai, lekin koi catastrophe nahi.

Soft deadline — miss hone ka consequence?

Result ki reduced/degrading value rehti hai; kabhi-kabhi misses tolerate hoti hain.

WCET kya hai aur ise (average ki jagah) kyun use karein?

Worst-Case Execution Time; deadlines worst case mein fail hoti hain, isliye guarantees maximum pe build honi chahiye, na ki mean pe.

Ek periodic task ki utilisation?

U_{i} = C_{i} / T_{i}

(CPU fraction jo woh demand karta hai).

n

tasks ki total utilisation?

U = \sum_{i} C_{i} / T_{i}

; agar

U > 1

toh CPU over-subscribed hai aur miss unavoidable hai.

Liu–Layland RM schedulability bound?

U \leq n (2^{1/ n} - 1)

; limit

\to ln 2 \approx 0.693

jab

n \to \infty

Ek CPU pe EDF utilisation bound?

U \leq 1

(EDF periodic single-processor ke liye optimal hai).

Kya RM utilisation test sufficient hai ya necessary?

Sirf Sufficient — ise fail karna unschedulability prove nahi karta; exact Response-Time Analysis use karo.

Response-Time Analysis equation?

R_{i} = C_{i} + \sum_{j \in h p (i)} ⌈ R_{i} / T_{j} ⌉ C_{j}

, convergence tak iterate karo; schedulable iff

R_{i} \leq D_{i}

⌈ R_{i} / T_{j} ⌉

kyun aata hai?

Yeh count karta hai ki higher-priority task

j

, task

i

R_{i}

ke during kitni baar preempt karta hai.

Hard real-time goal ek word mein?

Predictability (bounded worst case), raw speed nahi.

Recall Feynman: 12-saal ke bachche ko explain karo

Socho school bus pakadna. Hard deadline: ek second bhi late ho toh bus chali jaati hai aur school miss — disaster. Firm deadline: aap aa toh sakte ho, lekin late aaye toh homework "count nahi hoga" — koi points nahi, lekin kisi ko hurt nahi; bas throw away karo. Soft deadline: thoda late aana allowed hai aur phir bhi zyaadatar marks milenge, bas jitna late, utne kam. Yeh promise karne ke liye ki hard bus kabhi miss nahi hogi, aap "main fast bhaagunga" nahi kehte — aap slowest chalak speed measure karte ho, ek door use karne wale sabhi logon ko jodते ho, aur prove karte ho ki aap sab time pe fit ho jaate ho. Fast-on-average koi promise nahi hai; worst case use karke proof hai.

Connections

Rate-Monotonic Scheduling
Earliest Deadline First (EDF)
Worst-Case Execution Time analysis
Priority Inversion and Priority Inheritance
RTOS scheduler design
Periodic vs Aperiodic Tasks
Jitter and Latency