Communication interfaces — UART, SPI, I2C (master - slave), CAN bus

5.5.5 · Coding › Embedded Systems & Real-Time Software

4 interfaces ek nazar mein

Interface	Wires	Clock?	Topology	Typical speed	Killer feature
UART	2 (TX, RX)	❌ async	point-to-point	~115.2 kbps	dead simple, no clock
SPI	4 (MOSI, MISO, SCLK, SS)	✅	1 master, many slaves (SS per slave)	10s of Mbps	fastest, full-duplex
I2C	2 (SDA, SCL)	✅	multi-master, addressed	100k/400k/3.4M	sirf 2 wires mein kai devices
CAN	2 (CANH, CANL diff)	❌ (self-clocking)	multi-master bus	1 Mbps (classic)	noise-immune, prioritised, automotive

1. UART — Universal Asynchronous Receiver/Transmitter

Frame anatomy (HOW ek byte travel karti hai):

idle(HIGH) | START(0) | D0 D1 D2 D3 D4 D5 D6 D7 | [PARITY] | STOP(1) | idle

Line HIGH idle rehti hai. Ek falling edge (START=0) receiver ko jagaati hai.
Receiver 1.5 bit-times wait karta hai, phir har 1 bit-time pe sample karta hai → mid-bit par land karta hai (slight clock error ke liye robust).
LSB pehle aata hai.

2. SPI — Serial Peripheral Interface

4 wires: MOSI (Master Out Slave In), MISO (Master In Slave Out), SCLK, SS.

CPOL/CPHA (mashhoor 4 modes):

CPOL = idle clock level (0 = idle low, 1 = idle high).
CPHA = kaunsa edge sample karta hai (0 = pehle edge par sample, 1 = doosre edge par sample).

Mode	CPOL	CPHA	Sample edge
0	0	0	rising
1	0	1	falling
2	1	0	falling
3	1	1	rising

3. I2C — Inter-Integrated Circuit

Protocol grammar (HOW ek transfer frame hoti hai):

START: SDA HIGH SCL ke dauran fall karta hai (ek unique illegal-during-data event).
STOP: SDA HIGH SCL ke dauran rise karta hai.
Data sirf tab change hoti hai jab SCL LOW ho; SCL HIGH hone par valid/sampled hoti hai.
Har 8 bits ke baad receiver 1 clock ke liye SDA low pull karta hai = ACK (HIGH = NACK).
Pehla byte = [7-bit address][R/W bit].

4. CAN — Controller Area Network

Bitwise arbitration (HOW collisions bina retransmit ke resolve hoti hain):

Bus wired-AND hai: dominant (0) recessive (1) ko override karta hai (jaise I2C ka wired-AND).
Har transmitter apna ID bhejta hai aur bus ko saath mein sunता hai.
Agar koi node recessive(1) bheje par dominant(0) padhe, toh woh haar gaya → instantly back off karta hai, sunna jaari rakhta hai.
Numerically sabse chhote ID wala node (sabse zyada leading dominant bits) jeetta hai aur bina kisi corruption ke continue karta hai. Yeh non-destructive arbitration hai — jeetnewala message kabhi re-send nahi hota.

Flashcards

UART ka full form kya hai aur "asynchronous" kyun?

Universal Asynchronous Receiver/Transmitter; koi shared clock wire nahi — dono sides pehle baud par agree karti hain aur start bit + timing use karti hain.

UART frame ki shuruat kya mark karta hai aur kyun?

Ek START bit (line idle HIGH se LOW ho jaati hai); yeh "starting gun" hai taki receiver jaane kab bit-timing shuru karni hai.

Approx UART clock tolerance aur ~5% kyun?

±~5.3%;

9.5 ε t_{bi t} < 0.5 t_{bi t}

se — error last sample se pehle up to 9.5 bit-times mein accumulate hoti hai.

SPI ki 4 lines batao.

MOSI, MISO, SCLK, SS (chip select, active low).

SPI ko har slave ke liye ek SS line kyun chahiye?

SPI mein koi addressing nahi; master kisi device ko select karne ka ek hi tarika hai — us device ki SS low pull karna.

CPOL aur CPHA kya control karte hain?

CPOL = idle clock polarity; CPHA = kaunsa clock edge data sample karta hai (pehla vs doosra).

SPI full-duplex kyun hai?

Master aur slave shift registers ek ring banate hain — har clock edge ek bit bahar bhejta hai (MOSI) aur ek bit andar leta hai (MISO) saath mein.

I2C lines open-drain with pull-ups kyun honi chahiye?

Kai devices ek wire share karte hain; open-drain sirf LOW pull ya float kar sakta hai, toh do drivers kabhi short nahi hote — wired-AND, LOW hamesha jeetta hai.

I2C ka pehla byte kya hota hai?

7-bit slave address + 1 R/W bit; receiver ACK karta hai SDA ko ek clock ke liye low pull karke.

I2C pull-up resistor size kaise karein?

Upper bound

R_{p} < t_{r, ma x} / (0.85 C_{b})

itna fast rise ke liye; lower bound

R_{p} > (V_{cc} - V_{O L}) / I_{O L}

itna low pull karne ke liye.

CAN dominant vs recessive bit kya hota hai?

Dominant = 0 (override karta hai), recessive = 1; wired-AND toh dominant hamesha jeetta hai.

CAN simultaneous transmissions retransmission ke bina kaise resolve karta hai?

Bitwise non-destructive arbitration: jo node recessive bheje par dominant padhe woh haarta hai aur drop out karta hai; sabse chhota ID (highest priority) intact jeetta hai.

High bit rate par CAN bus length kyun limited hai?

Ek node ko arbitration loss detect karne ke liye ek bit time mein bus round-trip sunni padti hai:

t_{bi t} \geq 2 L / v

CAN noise-immune kyun hai?

Differential signaling — common-mode noise dono wires par equally hit karti hai aur

V_{C A N H} - V_{C A N L}

mein cancel ho jaati hai.

Recall Feynman: 12-saal ke bachche ko samjhao

Sochho chips notes pass kar rahi hain. UART: do dost, koi shared clock nahi — woh agree karte hain "ek letter har second padhenge," ek desk thokta hai kehne ke liye "abhi shuru kar." SPI: ek boss metronome ke saath; jis par boss point kare (SS) woh boss ke saath har tick par ek note trade karta hai — super fast par boss ko har dost ki taraf alag finger chahiye. I2C: ek party line par class — sabse pehle apna naam whisper karte hain ("address"), sirf matching baccha jawaab deta hai, aur rule hai "agar koi quiet bole (LOW), toh quiet hai." CAN: noisy room mein bacche numbers shouting karte hain; sabse chhote number wala baccha hamesha jeetta hai aur apna sentence finish karta hai, aur kyunki woh sab do cups se whisper karte hain, room noise cancel ho jaati hai.

Connections

Serial vs Parallel communication
Open-drain vs Push-pull outputs
Shift registers (SPI ka core)
Differential signaling & noise immunity
Bit stuffing & CRC in CAN frames
Interrupts vs Polling (MCUs in peripherals ko kaise service karte hain)
Baud rate & clock generation (timers/PLL)
Wired-AND logic (I2C aur CAN arbitration dono mein shared)