5.5.3 · HinglishEmbedded Systems & Real-Time Software

Timers — PWM generation, input capture, output compare

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5.5.3 · Coding › Embedded Systems & Real-Time Software


1. Counter — first principles

PRESCALER KYU? Peripheral clock (maano 72 MHz) aksar bahut fast hoti hai. Ek prescaler usse divide karta hai taaki har tick ek usable time tak chale.


2. PWM generation (ek special output-compare mode)

HARDWARE YEH KAISE BANATA HAI: har tick pe yeh CNT ko Capture/Compare Register CCR se compare karta hai:

  • Jab tak CNT < CCR → pin HIGH hai
  • Jab CNT ≥ CCR → pin LOW hai
  • Wrap pe (CNT = ARR+1 → 0) → pin wapas HIGH ho jaati hai.

Toh CCR set karta hai ki HIGH kitni der raha, ARR set karta hai pura period.

Figure — Timers — PWM generation, input capture, output compare

3. Output Compare (general)


4. Input Capture


5. Common mistakes (Steel-man + fix)


6. Active recall

Recall Feynman: ek 12-saal ke bachche ko samjhao

Socho ek ghadi ki sui baar baar ek circle mein ghoom rahi hai. PWM: tum ek bulb ko bolte ho "jab tak sui pehli quarter mein hai, jali rehna, baaki off" — sui ko tez ghuma do aur bulb bas half-bright dikhega; "off line" ko move karo dimming ke liye. Input capture: ek dost table thapta hai, aur tum exactly likh lete ho us waqt ghadi ki sui kahan thi. Do baar thapo, dono positions dekho, aur tumhe pata chal jaata hai gap kitna tha — bina khud stopwatch ghurte. Ghadi (timer) dekh rahi hai; tum bas notes padhte ho.


Connections

  • GPIO and Alternate Functions — PWM/compare pins ko AF mode enable karna padta hai.
  • Interrupts and NVIC — capture/compare events ISRs fire karte hain; overflow tracking.
  • Clock Tree and Prescalers kahan se aata hai.
  • Motor Control and H-Bridges — PWM speed drive karta hai; dead-time gaps insert karta hai.
  • Servo and ESC Control — PWM ki pulse-width interpretation.
  • Encoder Mode — timer quadrature count karta hai; input capture ka cousin.
Timer period formula in terms of PSC, ARR, f_clk
PSC pe +1 kyun?
Taaki PSC=0 clock ko 1 se divide kare, 0 se nahi (divider hai PSC+1).
ARR pe +1 kyun?
Counter count 0 ko include karta hai, toh ARR+1 ticks per cycle hoti hain.
PWM duty cycle formula
.
PWM period aur duty kaun set karta hai?
ARR period set karta hai; CCR HIGH duration (duty) set karta hai.
Output compare data direction
Timer → Pin (CNT, CCR tak pahunchta hai, hardware pin pe act karta hai).
Input capture data direction
Pin → Timer (edge event CNT ko CCR mein copy karta hai).
Do captures se period (overflow ke saath)
.
Toggle-mode output frequency vs match rate
Output freq = match-rate / 2 (do toggles per period).
72 MHz pe 1 kHz 50% PWM ke liye settings
PSC=71 (1 MHz), ARR=999, CCR=500.
50 Hz pe servo 1.5 ms center pulse, 1 µs ticks
ARR=19999, CCR=1500.
Negative capture difference ka fix
(c2−c1) modulo (ARR+1) lo counter wrap account karne ke liye.

Concept Map

divided by PSC+1

sets tick rate f_tim

wraps at ARR

sets period T

compared to CCR

CNT lt CCR HIGH else LOW

D equals CCR over ARR+1

Time drives Pin

snapshots counter

Pin drives Time

done in hardware

done in hardware

Peripheral clock f_clk

Prescaler PSC

Counter CNT

Auto-Reload ARR

PWM period

Compare Reg CCR

Output pin

Duty cycle

PWM / Output Compare

External pin edge

Input Capture

CPU free, exact timing