Memory model — happens-before, acquire-release semantics

5.2.27 · Coding › C++ Programming

WHY memory model exist karta hai?

WHY reordering hota hai (teen layers):

Compiler optimization ke liye reorder karta hai (register allocation, hoisting).
CPU out-of-order aur speculatively execute karta hai.
Cache/store buffers delay karte hain jab ek write doosre cores ko visible hoti hai.

Ek naive flag jaise bool ready = true koi guarantee nahi deta ki woh data jo aapne usse pehle likha, woh visible hoga jab doosra thread ready == true dekhe. Yahi woh bug hai jo acquire-release fix karta hai.

Happens-before: core relation

Acquire-Release: ek happens-before edge banana

Figure — Memory model — happens-before, acquire-release semantics

Worked example Canonical message-passing pattern

int data = 0;                          // plain, non-atomic
std::atomic<bool> ready{false};
 
// Thread 1 (producer)
data = 42;                                       // (1)
ready.store(true, std::memory_order_release);    // (2) RELEASE
 
// Thread 2 (consumer)
while (!ready.load(std::memory_order_acquire))   // (3) ACQUIRE
    ;
assert(data == 42);                              // (4) ALWAYS holds

(4) kyun guaranteed hai:

(1) sequenced-before (2) hai (same thread, program order) — Kyun? release (1) ko (2) ke neeche jaane se rokta hai.
(2) synchronizes-with (3) hai (release store ko acquire load ne read kiya) — Kyun? yahi acquire-release pair ki definition hai.
(3) sequenced-before (4) hai.
Chain: (1) →hb (2) →hb (3) →hb (4), toh (1) happens-before (4) ⇒ thread 2 data == 42 dekhega. data par koi data race nahi kyunki hb edge dono accesses ko order karta hai.

Worked example Kyun

memory_order_relaxed isse todta hai

data = 42;
ready.store(true, std::memory_order_relaxed);   // relaxed!
// ... consumer with relaxed load ...
assert(data == 42);   // MAY FAIL

Yeh step kyun fail karta hai: relaxed sirf atomicity deta hai — koi synchronizes-with edge nahi. Toh data = 42 aur consumer ke beech koi happens-before nahi. data ka store ready ke baad visible ho sakta hai, ya data ka read ek stale cached value use kar sakta hai. Assert fire ho sakta hai.

Ordering ladder (har tag KYA karta hai)

Rule ko first principles se derive karna

Common mistakes (Steel-man + fix)

Recall Feynman: 12-saal ke bacche ko samjhao

Do dost notes pass karte hain. Ravi ek kaagaz par ek secret likhta hai (data), phir mailbox par ek flag lagata hai (atomic). Maya mailbox check karti rehti hai; jis pal woh flag dekhe, is game ka rule guarantee karta hai ki secret andar hai — woh kabhi khaali box nahi kholegi. "Flag lagao" = release (pehle likhna khatam karo, phir signal do). "Flag dekho aur kholo" = acquire (signal dekhte hi, aap sab kuch padh sakte ho). Agar yeh rules skip karo (relaxed), Maya flag dekh sakti hai lekin box khol sakti hai Ravi ke likhna khatam karne se pehle — garbage milega. Flag tabhi kaam karta hai jab Maya wahi exact flag dekhe jo Ravi ne uthaya — yahi "stored value ko read karna zaruri hai" hai.

Flashcards

C++ mein data race kya hota hai aur iska kya consequence hai?

Do threads same memory location access karte hain, ≥1 likhta hai, unke beech koi happens-before ordering nahi. Yeh undefined behavior hai.

Happens-before relation define karo.

Sequenced-before (intra-thread) aur synchronizes-with (cross-thread atomic edges) ka transitive closure. Agar A hb B hai, toh B A ke saare side effects dekhta hai.

Release-store kab acquire-load ke saath synchronize karta hai?

Jab acquire-load woh value padhta hai jo release-store ne likhi thi (ya uski release sequence mein baad ki value).

memory_order_release kaunsi ordering guarantee karta hai?

Store se pehle koi memory operation us ke baad reorder nahi ho sakti (downward barrier); uske pehle ki writes matching acquire ko visible ho jaati hain.

memory_order_acquire kaunsi ordering guarantee karta hai?

Load ke baad koi memory operation us se pehle reorder nahi ho sakti (upward barrier); yeh publisher ki release se pehle ki writes dekhta hai.

memory_order_relaxed kya guarantee karta hai?

Sirf atomicity aur per-variable modification-order consistency — baaki kisi memory ki koi ordering NAHI, koi synchronizes-with edge nahi.

seq_cst, acq_rel se kaise stronger hai?

Yeh ek single global total order add karta hai jis par saare seq_cst operations agree karte hain, inconsistent observations ko rokta hai (jaise IRIW).

Edge banane ke liye acquire-load ko stored value kyun read karni chahiye?

Synchronization data flow follow karta hai; agar load ne purani value paadhi toh usne release observe nahi kiya, toh writer ka pehle ka kaam inherit nahi karta.

Message-passing example mein assert(data==42) guaranteed kyun hai?

data=42 →(seq-before) release-store →(sync-with) acquire-load →(seq-before) assert, ek hb chain banta hai toh reader data dekhta hai.

Connections

std-atomic and atomic operations
Mutexes and locks (mutex provides acquire on lock, release on unlock)
Out-of-order execution and store buffers (CPU)
Compiler reordering and the as-if rule
Lock-free programming patterns
Sequential consistency vs weak memory models
std-atomic_thread_fence