Race condition — example, why it's a problem

4.2.13 · Coding › Operating Systems

WHAT is a race condition?

Teen ingredients SAARE present hone chahiye:

Shared data (ek variable, file, counter, struct).
Concurrent access (≥2 threads/processes interleaved chalte hue).
Kam se kam ek writer (read-only sharing hamesha safe hoti hai).

Agar koi ek missing hai → koi race nahi.

WHY does it happen? (first-principles derivation)

Key insight: counter++ jaisi line atomic nahi hai. CPU memory ko ek indivisible step mein increment nahi kar sakta. Compiler isse teen machine instructions mein tod deta hai:

counter++ \equiv read LOAD R \leftarrow co u n t er; modify ADD R \leftarrow R + 1; write STORE co u n t er \leftarrow R

Ye ek read–modify–write (RMW) sequence hai. Har thread ka apna private register $R$ hota hai. OS scheduler kisi bhi point par thread ko preempt kar sakta hai — in teeno steps ke beech mein bhi.

The canonical EXAMPLE

Do threads dono counter++ 1 baar chalate hain, starting se counter = 5. Expected final value: $7$ .

Figure — Race condition — example, why it's a problem

Worked example Ek "bad" interleaving jo ek update kho deti hai

Step	Thread A	Thread B	A's $R$	B's $R$	`counter`
1	LOAD R←counter		5	–	5
2		LOAD R←counter	5	5	5
3	ADD R←R+1		6	5	5
4		ADD R←R+1	6	6	5
5	STORE counter←R		6	6	6
6		STORE counter←R	6	6	6

Ye step (step 2) kyun? B ko A ke RMW ke beech mein schedule kiya gaya. B stale value 5 padhta hai. Result = 6, 7 nahi. Ek increment gayab ho gaya.

Worked example Ek "good" (serialized) interleaving — same code, sahi answer

Step	Thread A	Thread B	`counter`
1	LOAD R←5		5
2	ADD R←6		5
3	STORE		6
4		LOAD R←6	6
5		ADD R←7	6
6		STORE	7

Ye step kyun? Yahan A ka poora RMW B ke shuru hone se pehle khatam ho jaata hai. B fresh value 6 padhta hai → sahi 7 milta hai. Same code, alag timing, alag result — yahi race ki definition hai.

WHY it's a problem hai (sirf "kabhi kabhi galat" nahi)

HOW hum ise fix karte hain: critical section ko mutually exclusive banao (ek waqt mein sirf ek thread andar) lock/mutex use karke, ya phir atomic instruction use karo taaki RMW ek indivisible step ban jaye:

lock(m); counter++; unlock(m);     // mutual exclusion
// or
atomic_fetch_add(&counter, 1);     // hardware-atomic RMW

Common mistakes (Steel-man + fix)

Flashcards

Race condition ke liye kaunse teen ingredients sab zaroori hain?

Shared mutable state + concurrent access + kam se kam ek writer.

counter++ atomic kyun nahi hai?

Ye ek read–modify–write mein compile hota hai: LOAD, ADD, STORE — teen alag interruptible machine instructions, har thread apna register use karta hai.

Critical section kya hai?

Code ka woh region jo shared state access karta hai aur jise mutual exclusion ke saath chalna chahiye.

Lost-update example mein do counter++ 5 se shuru karke, kaun si galat value aa sakti hai aur kyun?

7 ki jagah 6 — dono threads 5 LOAD karte hain kisi ke bhi STORE karne se pehle, isliye doosra STORE pehle wale ko overwrite kar deta hai, ek increment kho jaata hai.

1000 baar tests pass hone se race absent hona prove kyun nahi hota?

Races probabilistic hoti hain; hit probability p per run ke saath, P(no failure)=(1−p)^n high reh sakta hai even jab bug real ho.

volatile counter race ko fix kyun NAHI karta?

Ye sirf compiler register-caching rokta hai; ye RMW ko atomic nahi banata aur na hi mutual exclusion deta hai.

TOCTOU race kya hai?

Time-Of-Check-To-Time-Of-Use: condition check karne aur us par act karne ke beech state badal jaati hai (e.g. file permission check phir open), security ke liye exploitable.

N unsynchronized counter++ 0 se, possible final values ka range kya hai?

2 aur N ke beech — correct N hai, lekin adversarial interleavings ise 2 tak gira sakti hain.

Counter race khatam karne ke do sahi tarike?

(1) Critical section ke around lock/mutex se mutual exclusion; (2) hardware-atomic RMW jaise atomic_fetch_add.

Race ko "Heisenbug" kyun kehte hain?

Isse observe karna/slow karna (e.g. prints add karna) timing badal deta hai aur bug ko disappear kara sakta hai, isliye ye debugging se bacha rehta hai.

Recall Feynman: 12-saal ke bacche ko samjhao

Socho tum aur tumhara dost ek cookie jar share karte ho aur ek notepad jisme likha hai kitni baqi hain: 5. Tum dono "5" padhte ho, dono ek lete ho, aur dono note ko "4" (5−1) update karna chahte ho. Lekin update karne ka matlab hai: 5 padho → "4" socho → 4 likho. Agar tumhara dost "5" padhta hai jab tum abhi soch rahe ho, woh bhi "4" likhta hai. Do cookies gayi, lekin note abhi bhi 3 ki jagah 4 kehta hai. Note galat hai — aur galat hoga ya nahi ye depend karta hai kaun same moment par dekhta hai. Fix: notepad par lock lagao taaki sirf ek hi banda ek baar padh-aur-likh sake.

Connections

Critical Section Problem
Mutex and Locks
Atomic Operations
Semaphores
Deadlock (fix ka ek hazard hai, race ka nahi)
TOCTOU Vulnerabilities
Memory Consistency Models
Scheduler and Preemption