Intuition The one core idea
When two or more independent workers (threads) read and write to the same shared notebook (memory), the exact order in which their scribbles become visible to each other is not guaranteed to match the order they were written. A memory model is simply the written rulebook that tells you which visible orderings are legal — and everything on the parent page is just naming, testing, and taming those legal reorderings.
This page assumes you have seen nothing . We build every word the parent note uses, one brick at a time, before you ever meet SC, TSO, or a fence.
A thread is a single stream of instructions being executed one after another, like one person reading a to-do list top to bottom. A program can run several threads at once, and they share the same memory.
Picture two people, each holding their own paper list, both allowed to write into and read from one shared whiteboard in the middle of the room.
Intuition Why the topic needs this
With one worker, order is obvious — there is only one list. The moment there are two lists, "what order did things happen in?" stops having one answer. Memory models exist only because of multiple threads.
Definition Memory location / variable
A memory location is one named storage box that holds a value. We write x , y , flag , data for the names (addresses) of these boxes. Writing x = 1 means "put the value 1 into the box named x ".
Think of the whiteboard as a grid of labelled boxes. x and y are two different boxes.
Intuition Why "different addresses" matters
The whole subtlety of memory models is about ordering operations on different boxes (x then y ). Ordering of operations on the same box is handled separately (that is "coherence", section 8). Keep this split in your head from now on.
Definition Store (write) and Load (read)
A store is putting a value into a box: x = 1 . A load is reading the value out of a box into a private scratch register: r 1 = y .
store(x=1) → hand writes 1 into box x.
load(y) → hand copies whatever box y currently holds onto your private notepad r1.
r1, r2
A register (r 1 , r 2 ) is a thread's private scratch value — nobody else can see it. It only ever gets filled by a load. When we ask "can r 1 == 0 ?" we are asking "could this thread have read a 0?".
Intuition Why these two verbs are enough
Every litmus test on the parent page is built out of just stores and loads . The entire subject is: in what order do stores become visible to other threads' loads?
Program order is the top-to-bottom order of instructions as written in one thread's source code. In
x = 1;
r1 = y;
x = 1 is before r1 = y in program order.
Common mistake The trap the whole topic is about
Program order (the order you wrote things) is not the same as the order other threads observe them happening. A memory model is precisely the map between "what I wrote" and "what you can see". Never assume they are equal on real hardware.
A reordering is when the hardware or compiler lets a later operation (in program order) take effect before an earlier one, as seen by other threads. Because there are two verbs, there are exactly four possible reorder pairs:
Store → Load , Store → Store , Load → Load , Load → Store
Read A → B as "A comes first in program order; can B overtake it?"
Intuition Why exactly four
Two operations, each is either a store or a load: 2 × 2 = 4 ordered pairs. The parent's big table has exactly these four rows — now you know where they come from. SC forbids all four; TSO allows only the first; Relaxed allows all four.
A store buffer is a small private waiting-list in front of each core. When a core does a store, it may drop the write into this buffer and move on immediately , before the value has reached the shared whiteboard. The core empties the buffer to the whiteboard later, at its own pace.
Intuition Why this single gadget explains TSO
Because a store can linger in the buffer, a later load (of a different box) can reach the whiteboard and finish first . That is exactly a Store→Load reordering — the one relaxation that separates TSO from SC. The parent's SB test result "r 1 == 0 ∧ r 2 == 0 " is just both stores sitting in buffers while both loads read the still-blank boxes.
Definition Store forwarding
A core can peek into its own store buffer, so it sees its own pending writes even before others do. This is why a thread never reads its own stale value — only other threads can.
Definition Total order / interleaving
A total order (or interleaving) is a single global timeline in which every operation from every thread is placed in one sequence, one after another, with no ties. Picture shuffling the two to-do lists into one master list, keeping each list's internal order.
Intuition Why this defines the strongest model
If you insist that some single shuffled timeline could have produced what everyone saw — and each thread's items stay in their own order — you have Sequential Consistency . It is the "as if one whiteboard, one hand, one clock" picture. Everything weaker exists because real hardware refuses to pay for a single global timeline.
Definition Cache coherence (per-location)
Coherence guarantees that for one single box , all threads agree on a single order of writes to that box, and nobody reads an older value after seeing a newer one. It says nothing about how two different boxes are ordered.
See Cache Coherence (MESI) for how hardware enforces this per box.
assumes coherence
Memory models take single-box order for granted (coherence handles it) and spend all their effort on the cross-box orderings from section 5. When the parent says "on different addresses", it means "the part coherence does not cover".
Definition Fence (barrier)
A fence is a special instruction that forces ordering: operations before it must complete/become visible before operations after it. On x86, MFENCE drains the store buffer — it makes pending stores hit the whiteboard before the next load runs.
Intuition Why fences appear everywhere later
A fence is the programmer's tool to buy back an ordering the model gave away. The parent's fix for the SB test (MFENCE) and the MP test (release/acquire, DMB) are all "put a wall here". Details live in Memory Barriers and Fences and C++ Atomics and memory_order .
A litmus test is the minimal two-thread program designed to expose one specific reordering, so we can ask "is this final outcome legal?". A memory model is fully described by which litmus outcomes it permits .
Small enough to enumerate every interleaving by hand, so the yes/no answer is airtight. The parent uses SB (tests Store→Load) and MP (tests Store→Store / Load→Load). You will never understand a model by staring at real code — you understand it through litmus tests.
Store and Load = the two verbs
Memory box x y = shared whiteboard
Program order = written order
Store buffer = private wait list
Total order = one timeline
Coherence = per box always
Litmus test = smallest experiment
Memory Models SC TSO Relaxed
Everything on the left is a foundation; they all funnel into the parent topic Memory Models . Prerequisites Store Buffers and Out-of-Order Execution and Happens-before and Synchronizes-with extend the store-buffer and total-order ideas.
Self-test: cover the right side and answer aloud.
What is a thread, in one picture? One worker reading a private to-do list, top to bottom, sharing a whiteboard with others.
What is the difference between a store and a load? Store writes a value into a shared box; load reads a box's current value into a private register.
What is program order? The top-to-bottom order of instructions as written in a single thread's source.
Why is program order NOT what other threads observe? Hardware and compilers may let a later operation take effect before an earlier one (reordering).
How many reorder pairs exist and why? Four — Store/Load × Store/Load, since each of two ops is one of two verbs.
What does a store buffer do? Holds a store privately so the core moves on before the write reaches shared memory, enabling Store→Load reordering.
What is store forwarding? A core can read its own pending buffered stores, so it never sees its own writes as stale.
What is a total order / interleaving? One global timeline placing every thread's operations in a single sequence, keeping each thread's internal order.
What does coherence guarantee, and what does it NOT? Guarantees a single agreed order of writes to ONE box; says nothing about ordering across different boxes.
What does a fence like MFENCE do? Forces ordering — drains the store buffer so earlier stores become visible before later operations run.
What is a litmus test? The minimal multi-thread program exposing one specific reordering, used to define which outcomes a model allows.