Intuition The ONE core ideaA computer normally does arithmetic on one number at a time . SIMD widens that so one single instruction chews through many numbers side-by-side — because those numbers are packed into one very wide register and the hardware runs parallel copies of the same adder. Everything else on the parent page is just counting how many fit and why the real-world speedup is smaller than that count .
Before you can read the parent note, you must be able to look at a symbol like ymm0, _mm256_add_ps, or e W see a picture . This page builds every one of those from nothing.
Definition Bit and byte — the atoms
A bit is a single 0-or-1 switch. Picture one lightbulb: off or on.
A byte is 8 bits glued in a row. Picture 8 lightbulbs in a strip.
Width in bits just means how many lightbulbs long something is.
Why the topic needs this: SIMD is entirely about how wide a register is. Every number in this chapter — 128, 256, 512 — is a bit count , a length measured in lightbulbs.
Multiply by 8. So 128 bits = 16 = 32 = 64
A register is a tiny box of bits inside the CPU that it can read and write instantly (much faster than RAM). A normal integer register is 64 bits wide — big enough for one number.
Now the key move. A vector register is a register that is deliberately much wider than one number so several numbers can sit inside it at once.
Intuition The strip pictureImagine a strip of pixels. A 64-bit box holds one number. A 256-bit box is 4× longer — you can lay several numbers end-to-end inside it with no gaps. That "laying end-to-end" is the whole trick.
Why the topic needs this: SSE/AVX/AVX-512 are just three widths of these boxes. The parent's names xmm (128), ymm (256), zmm (512) are the labels of these wide boxes.
This is the heart of every formula on the parent page, so we go slow.
Definition Element, packed, lane
An element is one individual number you care about (e.g. one pixel value, one audio sample).
Packed means "several elements laid end-to-end inside one wide register, no gaps."A lane is one element-sized slot in that register. The register is cut into equal lanes; each holds one element.
Intuition Why a "lane" is called a laneThink of a multi-lane highway. Each lane carries its own car (element), and cars in different lanes never collide. When the CPU does a packed add, every lane's adder fires at the same time , and no carry ever crosses a lane boundary — just like cars staying in their lane.
Worked example Reading the symbols out loudAVX register: W = 256 e = 32 32 256 = 8 literally what _mm256_add_ps means: 256-bit register, packed, single → 8 adds at once.
The parent page's suffixes come from how a number is stored in bits . See Floating Point Representation for the full story; here is only what you need.
Definition The two float sizes and their suffixes
Single precision float = 32 bits = "f32". Suffix s (as in ps = packed single ).Double precision float = 64 bits = "f64". Suffix d (as in pd = packed double ).Integer suffixes b/w/d/q = byte(8) / word(16) / dword(32) / qword(64) bits.
Why the topic needs this: e comes from the suffix . Same register, different element size, different lane count:
32 256 = 8 (ps) 64 256 = 4 (pd) pd code is "half as parallel" as ps code.
Definition Instruction and its overheadAn instruction is one command the CPU fetches from memory, decodes (figures out what it means), then executes . Fetch + decode is fixed overhead — you pay it whether the instruction touches 1 number or 8.
Intuition Why this makes SIMD a free-ish winA scalar loop pays fetch+decode once per number . A SIMD instruction pays it once per 8 numbers . Same overhead, 8× the useful work. This is exactly Data-Level Parallelism : the data differs across elements but the instruction is identical, so one decode can drive many lanes.
You never write raw SIMD by hand; you use intrinsics — C functions that map 1-to-1 to a machine instruction. Decode the name in pieces:
Definition Anatomy of an intrinsic_mm256_add_ps
_mm — SIMD intrinsic marker.256 — the register width W ymm, AVX).add — the operation.ps — element type: p acked s ingle → e = 32
Type name __m256 = "a 256-bit vector variable." _mm256_loadu_ps = load 8 floats into one; the u = unaligned (any address ok).
Why the topic needs this: the whole "HOW a vector add executes" section on the parent is just these decoded names. Once you can read the name, the code reads itself.
Two symbols on the parent page describe why you never actually get lanes× speedup.
f f fraction of your program's time that is vectorizable (can be sped up by SIMD). 1 − f Amdahl's law .
Intuition The second ceiling — memoryEven a perfect compute speedup is useless if the CPU can't fetch the numbers fast enough . Every element still has to travel from RAM. When RAM delivery is the bottleneck, adding lanes does nothing — this is the roofline idea, and it's why Cache and Alignment matters so much.
vector register xmm ymm zmm
float vs double suffix ps pd
instruction fetch decode overhead
SIMD one instruction many lanes
The map reads left-to-right: raw bits build the register, element size cuts it into lanes, the overhead argument motivates why one instruction should drive them all, and the two ceilings (f lanes.
Cover the right side and answer each:
A bit vs a byte A bit is one 0/1 switch; a byte is 8 bits.
256 bits is how many bytes? 32 bytes.
What is a register (vs RAM)? A tiny bit-box inside the CPU, read/written instantly, far faster than RAM.
What does "packed" mean? Several elements laid end-to-end in one wide register, no gaps.
What is a lane? One element-sized slot in a vector register; each fires its own adder in parallel.
Formula for lane count? lanes = W / e (register width bits ÷ element size bits).
Element size of f32 vs f64? 32 bits vs 64 bits.
What do the suffixes ps and pd mean? packed single (f32) and packed double (f64).
Why does one SIMD instruction beat a scalar loop? Fetch+decode overhead is paid once for many elements instead of once per element.
What does the _mm256 in an intrinsic name tell you? 256-bit register width → the AVX / ymm register.
What is f The fraction of runtime that is vectorizable.
Why is real speedup below lanes×? Non-vectorizable fraction (Amdahl) plus the memory-bandwidth ceiling.
Recall Quick self-test: AVX register holding doubles — how many lanes, and why not more?64 256 = 4
Once every line above feels obvious, the parent note SIMD — vector instructions, SSE - AVX will read as pictures, not symbols.
