Hum classic 5-stage MIPS pipeline use karte hain: IF (instruction fetch) → ID (decode + register read) → EX (execute/ALU) → MEM (memory access) → WB (write back to register file).
YE KYU HOTE HAIN: pipelining instructions ko time mein overlap karta hai, lekin real dependencies (data flow, control flow) sequential hoti hain. Overlap aur sequence ka collision → hazard.
Sabse common data hazard hai RAW (Read-After-Write): instruction j ek aisa register read karta hai jise instruction i (earlier wali) write karne wali hai.
KAISE — forwarding conditions (derive karo): EX mein ek instruction ke source registers rs, rt hote hain. Hum inhe aage wali do instructions ke destination registers se compare karte hain.
Resolve hone tak stall karo — hamesha penalty bharo. Simple, slow.
Predict not-taken — fall-through path fetch karte raho; galat hone par flush karo. Sasta, ~50% accurate.
Delayed branch — branch ke baad wali instruction ko regardless execute karo ("branch delay slot"). Compiler ise usefully fill karta hai. (Classic MIPS.)
Dynamic branch prediction — runtime par har branch ka behavior seekho.
States: 00 strong-NT → 01 weak-NT → 10 weak-T → 11 strong-T. Taken → increment (saturating at 11); Not-taken → decrement (saturating at 00). Taken predict karo agar top bit = 1.
Structural (hardware conflict), Data (value ready nahi, e.g. RAW), Control (branch ke baad next PC unknown).
Forwarding load-use stall kyu nahi hata sakta?
Load value sirf MEM ke end mein exist karti hai, lekin consumer ko EX mein chahiye time mein ek cycle pehle; tum data ko time mein peeche forward nahi kar sakte, isliye ≥1 stall rehta hai.
One-cycle stall implement karne ke teen kaam kya hain?
PC freeze karo (koi nayi fetch nahi), IF/ID register freeze karo, aur ID/EX control signals zero karke bubble insert karo.
EX-hazard forwarding condition (input A)?
EX/MEM.RegWrite ∧ EX/MEM.rd≠0 ∧ EX/MEM.rd = ID/EX.rs → EX/MEM ALU result forward karo.
EX/MEM (closer) forward ko MEM/WB pe priority kyu milti hai?
Agar do earlier instructions same register mein write karti hain, toh program order kehta hai ki most recent write sahi hai; EX/MEM mein newer value hoti hai, isliye woh jeetti hai.
Branch prediction ke saath effective CPI ka formula?
Loops ke liye 2-bit predictor 1-bit se behtar kyu hai?
Isme hysteresis hai: ek single anomaly (loop exit) prediction nahi paltati; do baar lagataar galat hona padta hai, isliye loops ~ek baar mispredict karte hain instead of do baar.
Branch delay slot kya hota hai?
Branch ke baad wali instruction position jo hamesha execute hoti hai; compiler ise useful kaam se fill karta hai branch penalty hide karne ke liye.
Forwarding/bypassing define karo.
Ek result ko pipeline latch (EX/MEM ya MEM/WB) se directly baad wali instruction ke ALU inputs tak route karna, register file skip karke stall avoid karne ke liye.
Recall Feynman: ek 12-saal ke bachche ko explain karo
Socho ek sandwich shop ki line jahan har worker ek step karta hai. Kabhi kabhi "cheese add karo" wale worker ko sauce chahiye hoti hai jo pichli sandwich pe abhi-abhi lagi — agar sauce pehle se counter par hai (ek latch), toh worker use seedha uthaa sakta hai fridge mein jaane aur wapas aane ka intezaar kiye bina (forwarding). Lekin agar sauce abhi bani hi ja rahi hai (memory se load), toh jaldi pakadna bhi kaam nahi aayega — tumhe ek beat wait karna hi hoga (stall). Aur jab ek customer suddenly apna order badal de (branch), toh line guess karti hai ki woh kya chahenge aur banana shuru kar deti hai. Ek accha guesser (2-bit predictor) apna guess tabhi badlta hai jab do baar lagataar galat ho, toh ek weird customer poori line ko nahi bigadta.
