4.1.7
Intuition Bada picture (WHY yeh exist karta hai)Ek CPU bahut seedha-saadha hota hai: usse sirf ek 32-bit number dikhta hai. Instruction format ek agreed-upon tarika hai un 32 bits ko meaning mein kaat-ne ka — kaun sa operation, kaun se registers, kya constant. Bina ek fixed layout ke, hardware yeh nahi jaan sakta tha ki bits 21–25 ek register number hain ya kisi constant ka hissa. Formats assembler (software) aur decoder (hardware) ke beech ka contract hain.
MIPS sirf 3 formats aur fixed 32-bit width kyun use karta hai, iska gehra reason yeh hai: yeh hardware ko decode karna trivial aur uniform bana deta hai. Har instruction usi tarah fetch hoti hai (PC += 4), aur same bit positions formats ke across reuse hote hain taaki same wires register file ko feed kar sakein. Yahi RISC philosophy hai: richness se zyada regularity.
Har MIPS instruction = exactly 32 bits. Pehle 6 bits (yani opcode ) decoder ko batate hain ki kaunsa format expect karna hai. Yahi master key hai.
R-type (Register): teen registers use karne wale operations — jaise add $t0,$t1,$t2. Opcode 0 hota hai; asli operation funct field mein hoti hai.I-type (Immediate): ek 16-bit constant ya memory offset wale operations — jaise addi, lw, sw, beq.J-type (Jump): ek 26-bit address ke saath unconditional jumps — jaise j, jal.
6 opcode 5 rs 5 rt 5 rd 5 shamt 6 funct
Intuition Yeh widths kyun hain?
5-bit register fields isliye kyunki MIPS mein 2 5 = 32 log 2 32 = 5 shamtlog 2 32 = 5 funct0 saari R-type ops ke liye overloaded hai, isliye ek doosra 6-bit field add ko sub se, and se... alag karta hai. Isse 2 6 = 64 Total: 6 + 5 + 5 + 5 + 5 + 6 = 32
rs, rt source registers hain; rd destination hai.
6 opcode 5 rs 5 rt 16 immediate
Intuition 16-bit immediate par kyun aate hain?Humne rd, shamt, funct (16 bits) chhod diye aur sab ek constant ko de diye. 6 + 5 + 5 + 16 = 32 rt destination ban jaata hai (jaise addi $rt, $rs, imm), aur loads/stores ke liye immediate ek byte offset hota hai: lw $rt, offset($rs).
beq I-type kyun reuse karta hai? — relative addressing ki genius
beq $rs,$rt,label ko compare karne ke liye do registers chahiye aur ek target bhi. Lekin 16 bits ek poora 32-bit address hold nahi kar sakta! Trick yeh hai: 16-bit immediate ek signed word offset relative to PC hota hai. Branch target = ( PC + 4 ) + ( imm × 4 )
6 opcode 26 address
Intuition 32-bit address ke liye 26 bits kyun?6 + 26 = 32 target = top 4 bits ( PC + 4 ) [ 31 : 28 ] ∥ 26 address ∥ 2 00 00 append kiye jaate hain kyunki instructions word-aligned hain (low 2 bits hamesha 0 hote hain — toh unhe store kyun karein?). Top 4 bits current PC se aate hain. Isse effective 4 + 26 + 2 = 32
add $t0, $s1, $s2 encode karo (R-type)
Registers: $s1=17, $s2=18, $t0=8. add ke liye: opcode=0, funct=32.
Slots: add rd, rs, rt → rd=$t0=8, rs=$s1=17, rt=$s2=18, shamt=0.
0 ( 6 ) ∣ 1 7 ( 5 ) ∣ 1 8 ( 5 ) ∣ 8 ( 5 ) ∣ 0 ( 5 ) ∣ 3 2 ( 6 ) 000000 10001 10010 01000 00000 100000
Yeh step kyun? Source order dhyan se dekho: instruction add $t0,$s1,$s2 mein destination pehle likha jaata hai, lekin binary mein rd beech mein hota hai. Assembler yeh reordering tumhare liye karta hai.
lw $t0, 32($s3) encode karo (I-type)
lw $rt, offset($rs) → rt=$t0=8, rs=$s3=19, imm=32. lw ke liye opcode = 35.
3 5 ( 6 ) ∣ 1 9 ( 5 ) ∣ 8 ( 5 ) ∣ 3 2 ( 16 ) 100011 10011 01000 0000000000100000
Yeh step kyun? rs base address register hai, immediate isme add hota hai. rt loaded word receive karta hai — toh rt yahan destination hai, stores mein uske source role ke ulta.
beq $t0,$t1, LABEL ka branch target jahan LABEL 5 instructions aage hai
Assembler offset words mein compute karta hai: target branch ke baad wali instruction se 5 instructions aage hai. beq ka PC = P P + 4 target = ( P + 4 ) + 5 × 4 = P + 24 ×4 kyun? Har instruction 4 bytes ki hoti hai; offset words mein store hota hai taaki reach maximize ho. Hardware 2 se left shift karta hai.
j 0x00400024
Neeche ke 2 bits (hamesha 0) chhod do aur byte address ke bits [27:2] ko 26-bit field ke roop mein lo.
0 x 00400024 = 0000 0000 0100 0000 0000 0000 0010 0100 0 x 100009 j=2.
Yeh step kyun? Hum low 2 bits ya top 4 bits kabhi store nahi karte — hardware unhe reconstruct karta hai, space bachate hue.
Common mistake "rd binary mein bhi pehla register hai."Kyun sahi lagta hai: Assembly mein tum destination pehle likhte ho (add $rd, $rs, $rt), isliye lagta hai ki bits mein bhi pehle hoga.
Fix: R-type binary mein order hai rs, rt, rd (sources pehle, destination teesra ). Assembler reorder karta hai. Bit order aur syntax order ko alag se memorize karo.
Common mistake "Branch offset bytes mein hai / absolute address hai."Kyun sahi lagta hai: Addresses usually byte addresses hote hain.
Fix: Branch immediates PC+4 ke relative signed word offsets hain, hardware unhe 4 se multiply karta hai. Jump fields bhi word-shifted hain. Store ki gayi value ko hamesha 4 se multiply karo.
Common mistake "J-type memory mein kahin bhi jump kar sakta hai."Kyun sahi lagta hai: 26 bits + 2 implied = 28 lagta hai — 32 ke karib.
Fix: Top 4 bits current PC se aate hain , isliye j sirf usi 256 MB region ke andar reach kar sakta hai. Aage jaane ke liye jr chahiye (jump register, ek R-type jo poora 32-bit register value use karta hai).
Recall Feynman: ek 12-saal ke bacche ko explain karoSocho ek 32-light switchboard hai. Pehle 6 switches ek code word spell karte hain jo batata hai ki yeh kis tarah ka message hai. Agar yeh "teen lockers ke saath math karo" wala message hai, toh agle switches locker A, locker B, locker C ka naam lete hain aur ek chota extra code batata hai ki kaun sa math (add? subtract?). Agar yeh "ek chote number ke saath kuch karo" wala message hai, toh kam switches lockers ka naam lete hain aur baaki number spell karte hain. Agar yeh "door kahi jump karo" wala message hai, toh almost saare switches jagah spell karte hain. Same 32 switches, teen alag rulebooks — aur pehle 6 switches hamesha batate hain ki kaun sa rulebook use karna hai.
Mnemonic Teeno formats yaad karo"R egisters R ule, I mmediate I njects, J ust J ump."
R = 3 regs + funct · I = 2 regs + 16-bit const · J = 26-bit address.
R-type ka field order: "Oh, Really Rotten Rascals Shun Funerals" = Opcode, Rs, Rt, Rd, Shamt, Funct.
MIPS register field kitne bits ka hota hai aur kyun? 5 bits, kyunki 2 5 = 32 log 2 32 = 5
Har MIPS instruction ki total width? 32 bits, fixed, uniform decoding ke liye.
Decoder ko kaun sa field batata hai ki instruction kis format mein hai? 6-bit opcode (opcode 0 ⇒ R-type, funct dekho).
R-type bit-field order MSB se? opcode(6), rs(5), rt(5), rd(5), shamt(6→5), funct(6).
Saari R-type ops opcode 0 kyun share karti hain? 6-bit funct field unhe alag karta hai (2 6 = 64
R-type mein destination register kaun sa hai? rd (teesra register field), chahe assembly mein pehle likha jaata hai.
I-type bit-field order? opcode(6), rs(5), rt(5), immediate(16).
lw $t0,32($s3) mein rs, rt, imm kya hai?rs=s 3 ( ba se ) , r t =
beq ke liye branch target formula? target = (PC+4) + (signed_imm × 4).
Branch/jump offsets ko 4 se kyun multiply karte hain? Instructions word-aligned hain (4 ke multiples); word counts store karne se reach free mein badh jaati hai.
J-type fields aur target reconstruction? opcode(6)+address(26); target = PC[31:28] ‖ address ‖ 00.
Effective branch reach? ±128 KB (16 signed bits + 2 implied = 18-bit signed byte range).
j poori memory tak kyun nahi pahunch sakta?Top 4 bits current PC se aate hain ⇒ 256 MB region tak seemit; full 32-bit jumps ke liye jr use karo.
Shamt kya hai aur kitna wide hai? Shift amount, 5 bits (ek 32-bit word ke liye 0–31 positions).
MIPS Register File and Conventions — 32 registers kyun ⇒ 5-bit fieldsSingle-Cycle Datapath — fixed positions rs/rt ko hamesha register file feed karne dete hainControl Unit and Decoding — opcode/funct control signals drive karte hainSign Extension and Immediates — 16-bit imm 32-bit kaise banta haiPC-relative vs Absolute Addressing — branch vs jump target mathRISC-V Formats (R, I, S, B, U, J) — RISC-V hardware simplicity ke liye immediates kaise split karta hai
