Flip-flops — SR, D, JK — storing one bit

1.1.7 · Coding › How Computers Work

Flip-flop KYA hai?

Feedback memory KAISE banata hai (scratch se derive karo)

Do NOR gates se shuru karo. Yaad karo NOR: output 1 hota hai sirf tab jab dono inputs 0 hon.

$NOR (a, b) = \overline{a + b}$

Inhe cross-couple karo: har gate ka output doosre ke input mein feed karo. Yahi SR latch hai.

Inputs: $S$ (Set), $R$ (Reset).
Outputs: $Q$ aur $\overset{ˉ}{Q}$ .

$Q = \overline{R + \overset{ˉ}{Q}}, \overset{ˉ}{Q} = \overline{S + Q}$

Yeh yaad kyun rakhta hai? Maano $S = 0, R = 0$ . Equations mein daalo: $Q$ depend karta hai $\overset{ˉ}{Q}$ par, aur $\overset{ˉ}{Q}$ depend karta hai $Q$ par. Agar $Q = 1$ to $\overset{ˉ}{Q} = \overline{0 + 1} = 0$ , aur $Q = \overline{0 + 0} = 1$ ✓ — consistent. Agar $Q = 0$ to $\overset{ˉ}{Q} = 1$ aur $Q = \overline{0 + 1} = 0$ ✓ — yeh bhi consistent. Dono stable hain, toh circuit jo bhi pehle tha wahi hold karta hai. Wahi holding memory hai.

Figure — Flip-flops — SR, D, JK — storing one bit

NOR SR latch ki truth table

$S$	$R$	$Q_{n e x t}$	matlab
0	0	$Q$ (hold)	yaad rakhna
1	0	1	1 par Set
0	1	0	0 par Reset
1	1	forbidden	dono outputs 0, $Q = \overset{ˉ}{\overset{ˉ}{Q}}$ toot jaata hai

D flip-flop — forbidden state ko fix karna

KAISE: $R = \overset{ˉ}{S}$ force karo $S = D$ aur $R = \overline{D}$ tying karke. Ab $S = R = 1$ kabhi nahi ho sakta.

$Q_{n e x t} = D$

Ek clock daalo: sirf rising edge par $D$ sample karo. Edges ke beech value frozen rehti hai.

$D$	$Q_{n e x t}$
0	0
1	1

JK flip-flop — forbidden case ko useful banana

Hum ise current state se S aur R ko gate karke engineer karte hain: $S = J \overset{ˉ}{Q}, R = K Q$

Kyun? $J$ sirf tab set kar sakta hai jab $Q$ pehle se 0 ho ( $\overset{ˉ}{Q} = 1$ ); $K$ sirf tab reset kar sakta hai jab $Q$ pehle se 1 ho. Toh $S$ aur $R$ kabhi bhi dono 1 nahi hote — forbidden state structurally impossible hai.

$J$	$K$	$Q_{n e x t}$	matlab
0	0	$Q$	hold
0	1	0	reset
1	0	1	set
1	1	$\overset{ˉ}{Q}$	toggle

Common mistake Galat ideas ko steel-man karna

"Ek latch apni value hold karta hai kyunki kuch change nahi kar raha." Sahi lagta hai — lekin ek wire bhi tab tak nahi badlta jab tak tum use change nahi karte, phir bhi wire ki koi memory nahi hoti; source kato aur woh float karta hai. Asli reason hai feedback loop: latch apni khud ki value actively regenerate karta hai, toh woh tab bhi survive karta hai jab inputs "hold" state mein chale jaate hain. Fix: memory = self-sustaining feedback, sirf inactivity nahi.

"D flip-flop aur D latch same hain." Ek latch transparent hota hai jab bhi enabled ho (continuously $D$ follow karta hai). Ek flip-flop sirf clock edge par update karta hai. Fix: edge-triggering hi woh cheez hai jo registers ko bina glitches ke lockstep mein update karti hai.

" $J = K = 1$ illegal hai jaise $S = R = 1$ ." Analogy se tempting lagta hai. Lekin JK ko design hi kiya gaya tha ki woh case toggle ho. Fix: $J \overset{ˉ}{Q}, K Q$ gating simultaneous-set-reset ko hata deti hai, toh yeh safe hai.

Recall Feynman: 12-saal ke bacche ko explain karo

Socho ek light switch jo thoda special hai: iske paas do "push spots" hain, SET aur RESET. SET dabaao aur light ON rehti hai chahe tum haat hata lo. RESET dabaao aur woh OFF rehti hai. Woh "rehna" memory hai — switch yaad rakhta hai aakhri push. Clever part yeh hai ki do gates ek loop mein ek doosre ka answer phusphusaate hain, toh woh value hamesha ke liye repeat karte rehte hain. D version mein sirf ek button hai: jo bhi tum pakde ho (0 ya 1) jab ghanti (clock) baje, woh yaad rakhta hai. JK version mein ek magic combo bhi hai: dono buttons dabaao aur light flip ho jaati hai jo bhi thi uske ulte mein. 8 inhe stack karo aur tum ek poora number yaad rakh sakte ho — aise hi computer cheezein yaad rakhta hai!

Flashcards

Flip-flop ka minimal kaam kya hai?

Ek bit (ek akela 0 ya 1) store karna aur inputs badlne ke baad bhi hold karna.

Kaunsi property ek circuit ko "bistable" banati hai?

Iske paas do stable states hain jisme woh indefinitely rest kar sakta hai.

Kaunsi cheez bhulakkad gates ko memory mein badal deti hai?

Feedback (outputs ko inputs mein cross-coupling karna).

NOR SR latch: S=1,R=0 kya karta hai?

Q ko 1 par Set karta hai.

NOR SR latch: S=0,R=1 kya karta hai?

Q ko 0 par Reset karta hai.

NOR SR latch: S=0,R=0 kya karta hai?

Pehle wala Q hold karta hai (memory).

SR latch mein S=R=1 forbidden kyun hai?

Yeh Q=Q̄=0 force karta hai, Q ka Q̄ ka complement hona violate karta hai; release karne par race hoti hai.

D flip-flop forbidden state kaise avoid karta hai?

Yeh S=D aur R=NOT D set karta hai, toh S aur R kabhi dono 1 nahi hote.

D flip-flop ki characteristic equation?

Q_next = D.

JK flip-flop mein J=K=1 input kya karta hai?

Toggle: Q_next = NOT Q.

JK characteristic equation?

Q_next = J·Q̄ + K̄·Q.

JK forbidden state hatane ke liye kaise build kiya jaata hai?

Inputs ko S=J·Q̄ aur R=K·Q ke roop mein gate karo toh dono kabhi 1 nahi ho sakte.

Latch aur flip-flop mein kya farq hai?

Latch level-sensitive hai (enabled rehne par transparent); flip-flop edge-triggered hai.

8-bit register kis cheez se bana hota hai?

8 D flip-flops jo ek clock share karte hain, ek saath 8 bits capture karte hain.

Connections

Logic Gates — AND, OR, NOT, NAND, NOR — flip-flops NOR/NAND se bane hain
Boolean Algebra — characteristic equations derive karne ke liye use hoti hai
Clocks and Timing — edge-triggering aur synchronous design
Registers and RAM — flip-flops ki arrays jo words store karti hain
Counters and State Machines — JK toggle binary counters chalata hai
Combinational vs Sequential Logic — feedback = sequential