4.3.7 · D3Pretraining & Fine-Tuning LLMs

Worked examples — Parameter-efficient fine-tuning (PEFT)

2,773 words13 min readBack to topic

Recall the single formula everything on this page uses:

Every symbol above is used below. Nothing new is introduced without a picture.


The scenario matrix

Every LoRA question is really "count parameters" or "track a number through the equation" — but the setup varies along a few axes. Here is the full grid. Each cell gets its own worked example.

Cell Scenario class What makes it tricky Example
C1 Square matrix, standard The baseline; get the arithmetic reflex Ex 1
C2 Non-square matrix () and have different sizes Ex 2
C3 Degenerate LoRA vanishes — sanity limit Ex 3
C4 Limiting LoRA stops saving anything Ex 4
C5 scaling across ranks Keep update magnitude fixed Ex 5
C6 Init step-0 behaviour , forward equals base Ex 6
C7 Merge & zero-latency is one matrix Ex 7
C8 Storage / multi-task word problem Real GB-vs-MB budgeting Ex 8
C9 QLoRA memory exam twist 4-bit base + 16-bit adapters Ex 9
C10 Break-even rank exam twist When does LoRA stop being cheaper? Ex 10
Figure — Parameter-efficient fine-tuning (PEFT)

The figure above shows the sizes: the big frozen square , and beside it the two skinny strips (tall, columns) and (wide, rows). All examples are just measuring these shapes or pushing through them.


C1 — Square matrix, standard rank


C2 — Non-square matrix


C3 — Degenerate input:


C4 — Limiting case:


C5 — The scaling across ranks


C6 — Initialization at step 0


C7 — Merge and zero-latency inference


C8 — Storage word problem (multi-task)


C9 — QLoRA memory exam twist


C10 — Break-even rank exam twist


Active recall

Recall Which cell does each idea belong to?

Setting gives what update? ::: The zero matrix — pure base model (Cell C3). The rank where LoRA stops saving memory is? ::: (Cells C4, C10). Why does merging add zero latency? ::: is one matrix, same output (Cell C7). If you double , what keeps update strength fixed? ::: Double so is unchanged (Cell C5). In QLoRA which part is 4-bit? ::: Only the frozen base; adapters stay 16-bit (Cell C9).


Connections