Level 4 — Application

Transistors - BJT & FET

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Level 4 — Application (novel problems, no hints) Time limit: 60 minutes Total marks: 60

Use $...$ for inline math. Assume $V_T = 25\text{ mV}$ (thermal voltage) and $V_{BE(on)} = 0.7\text{ V}$ unless stated otherwise. Show all working.

Question 1 — BJT Switch Design (12 marks)

An NPN BJT drives a relay coil modelled as a $120\ \Omega$ resistor to a $12\text{ V}$ rail. The transistor has $\beta = 60$ (minimum guaranteed), $V_{CE(sat)} = 0.2\text{ V}$ , and $V_{BE(sat)} = 0.8\text{ V}$ . The base is driven from a $3.3\text{ V}$ microcontroller GPIO through a base resistor $R_B$ .

(a) Compute the collector current when the transistor is fully saturated. (2)

(b) Determine the minimum base current required to guarantee saturation, applying an overdrive factor of $3$ . (3)

(d) The GPIO can source at most $8\text{ mA}$ . Verify whether your chosen $R_B$ respects this limit, and state the resulting forced $\beta$ ( $\beta_{forced}$ ). (2)

(e) State one physical reason why operating deep in saturation slows the transistor's turn-OFF time. (2)

Question 2 — Common-Emitter Amplifier Analysis (14 marks)

A common-emitter amplifier uses voltage-divider bias: $V_{CC}=15\text{ V}$ , $R_1=47\text{ k}\Omega$ , $R_2=10\text{ k}\Omega$ , $R_C=2.2\text{ k}\Omega$ , $R_E=470\ \Omega$ (fully bypassed for AC). The BJT has $\beta=150$ .

(a) Find the DC base voltage $V_B$ using the Thévenin approximation, then $I_C$ . (4)

(b) Compute the transconductance $g_m$ and the small-signal input resistance $r_\pi$ . (3)

(d) A load $R_L = 4.7\text{ k}\Omega$ is now AC-coupled to the output. Recompute $A_v$ . (2)

(e) The bypass capacitor is removed. Re-derive the new gain expression and evaluate it. Comment on the trade-off. (2)

Question 3 — MOSFET Operating Point & Region (12 marks)

An NMOS transistor has $V_{th}=0.8\text{ V}$ , $k_n = \mu_n C_{ox}\frac{W}{L} = 0.5\text{ mA/V}^2$ , and $\lambda = 0$ . It is biased with $V_{GS}=2.0\text{ V}$ and a drain resistor $R_D = 3\text{ k}\Omega$ from $V_{DD}=10\text{ V}$ ; source is grounded.

(a) Assuming saturation, compute the drain current $I_D$ (use $I_D=\tfrac{1}{2}k_n(V_{GS}-V_{th})^2$ ). (3)

(b) Compute $V_{DS}$ and verify the saturation assumption is consistent. (3)

(d) $V_{GS}$ is now increased to $4.0\text{ V}$ . Show by calculation that the device has entered the triode region, and find the actual $I_D$ . (3)

Question 4 — Body Effect & Subthreshold Leakage (12 marks)

An NMOS device has zero-bias threshold $V_{th0}=0.5\text{ V}$ , body-effect coefficient $\gamma = 0.4\ \text{V}^{1/2}$ , and $2\phi_F = 0.7\text{ V}$ . The body-effect model is: $V_{th} = V_{th0} + \gamma\left(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F}\right)$

(a) Compute $V_{th}$ when $V_{SB} = 1.5\text{ V}$ . (3)

(b) In the subthreshold region, drain current follows $I_D = I_0\, e^{(V_{GS}-V_{th})/(nV_T)}$ with $n=1.5$ and $V_T=25\text{ mV}$ . By what factor does $I_D$ change if $V_{GS}$ drops by $100\text{ mV}$ below threshold? (3)

(d) Explain how the body-effect result in (a) worsens leakage control in stacked transistors, and how it is exploited in "reverse body bias" for low-power modes. (3)

Question 5 — Device Selection & Reasoning (10 marks)

(a) A designer must switch a $5\text{ V}$ , $2\text{ A}$ load with a $3.3\text{ V}$ logic signal and minimum static power. Choose between an enhancement NMOS ( $V_{th}=1.2\text{ V}$ , $R_{DS(on)}=25\text{ m}\Omega$ ) and an NPN BJT ( $\beta=100$ , $V_{CE(sat)}=0.3\text{ V}$ ). Justify your choice quantitatively (conduction loss and drive requirements). (5)

(b) Explain why a JFET and a depletion-mode MOSFET are both "normally-ON" devices, and give one circuit consequence of this property. (3)

Answer keyMark scheme & solutions

Question 1

(a) Saturated collector current: $I_C = \frac{V_{CC}-V_{CE(sat)}}{R_C} = \frac{12-0.2}{120} = \frac{11.8}{120} = 98.3\text{ mA}$ Why: In saturation $V_{CE}$ is fixed at $V_{CE(sat)}$ ; the coil resistance sets $I_C$ . (2)

(b) Base current at edge of saturation: $I_{B(edge)} = I_C/\beta = 98.3/60 = 1.64\text{ mA}$ . With overdrive factor 3: $I_B = 3\times1.64 = 4.92\text{ mA}$ . Why: Overdrive guarantees saturation despite $\beta$ /temperature spread. (3)

(c) $R_B = \dfrac{V_{GPIO}-V_{BE(sat)}}{I_B} = \dfrac{3.3-0.8}{4.92\text{ mA}} = \dfrac{2.5}{4.92\text{ mA}} = 508\ \Omega$ . Largest standard resistor below this: $R_B = 470\ \Omega$ (E12). (3)

(d) With $R_B=470\ \Omega$ : $I_B=(3.3-0.8)/470 = 5.32\text{ mA} < 8\text{ mA}$ → GPIO limit respected. $\beta_{forced}=I_C/I_B = 98.3/5.32 = 18.5$ . (2)

(e) In saturation both junctions are forward-biased, storing excess minority charge in the base (stored/saturation charge). Turn-off must first remove this charge before the collector current can fall → storage delay. (2)

Question 2

(a) $V_{th\acute e v}=V_{CC}\dfrac{R_2}{R_1+R_2}=15\times\dfrac{10}{57}=2.63\text{ V}$ , $R_{th}=R_1\|R_2=47\|10=8.25\text{ k}\Omega$ . $I_C \approx \dfrac{V_{th\acute ev}-0.7}{R_E + R_{th}/\beta}=\dfrac{1.93}{470+55}=\dfrac{1.93}{525}=3.68\text{ mA}$ . (Simplified ignoring $R_{th}/\beta$ : $I_C=1.93/470=4.11\text{ mA}$ — accept either; use $\approx4.0\text{ mA}$ .) (4)

Using $I_C=4.0\text{ mA}$ for the rest:

(b) $g_m = I_C/V_T = 4.0\text{ mA}/25\text{ mV}=160\text{ mA/V}=0.16\text{ S}$ . $r_\pi = \beta/g_m = 150/0.16 = 937\ \Omega$ . (3)

(c) With emitter bypassed: $A_v = -g_m R_C = -0.16\times2200 = -352$ . (3)

(d) $R_C\|R_L = 2.2\|4.7 = 1.5\text{ k}\Omega$ . $A_v=-g_m(R_C\|R_L)=-0.16\times1500=-240$ . (2)

(e) Unbypassed: $A_v = -\dfrac{g_m R_C}{1+g_m R_E}=-\dfrac{R_C}{1/g_m + R_E}\approx -\dfrac{R_C}{R_E}=-\dfrac{2200}{470}=-4.68$ . Trade-off: gain collapses dramatically but bandwidth, linearity and gain-stability improve (local negative feedback). (2)

Question 3

(a) $I_D=\tfrac12 k_n(V_{GS}-V_{th})^2=\tfrac12(0.5)(2.0-0.8)^2=0.25\times1.44=0.36\text{ mA}$ . (3)

(b) $V_{DS}=V_{DD}-I_D R_D = 10 - 0.36\times3 = 10-1.08 = 8.92\text{ V}$ . Saturation requires $V_{DS}\ge V_{GS}-V_{th}=1.2\text{ V}$ . Since $8.92>1.2$ ✓ consistent. (3)

(c) $g_m = k_n(V_{GS}-V_{th}) = 0.5\times1.2 = 0.6\text{ mA/V}$ . (Equivalently $g_m=\sqrt{2k_n I_D}=\sqrt{2\times0.5\times0.36}=0.6\text{ mA/V}$ .) (3)

(d) At $V_{GS}=4.0$ , assume saturation: $I_D=\tfrac12(0.5)(4-0.8)^2=0.25\times10.24=2.56\text{ mA}$ → $V_{DS}=10-2.56\times3=2.32\text{ V}$ . Overdrive $V_{GS}-V_{th}=3.2\text{ V} > V_{DS}=2.32$ → assumption fails, device is in triode. Solve triode: $I_D=k_n[(V_{GS}-V_{th})V_{DS}-\tfrac12 V_{DS}^2]$ with $V_{DS}=10-I_D R_D$ . Let $x=V_{DS}$ : $I_D=(10-x)/3$ (mA). $(10-x)/3 = 0.5[3.2x-0.5x^2]$ $(10-x)/3 = 1.6x - 0.25x^2$ $10-x = 4.8x - 0.75x^2$ $0.75x^2 -5.8x +10=0 \Rightarrow x^2 -7.733x +13.33=0$ $x=\dfrac{7.733\pm\sqrt{59.8-53.3}}{2}=\dfrac{7.733\pm2.55}{2}$ → $x=2.59\text{ V}$ (physical root <overdrive). $I_D=(10-2.59)/3 = 2.47\text{ mA}$ . (3)

Question 4

(a) $V_{th}=0.5+0.4(\sqrt{0.7+1.5}-\sqrt{0.7})=0.5+0.4(\sqrt{2.2}-\sqrt{0.7})$ $=0.5+0.4(1.483-0.837)=0.5+0.4(0.646)=0.5+0.258=0.758\text{ V}$ . (3)

(b) Factor $=e^{-100/(1.5\times25)}=e^{-100/37.5}=e^{-2.667}=0.0697\approx\tfrac{1}{14.4}$ . $I_D$ decreases by a factor of ~14 (drops to ~7% of threshold value). (3)

(c) Subthreshold swing = gate voltage change for one decade of $I_D$ : $S = n\,V_T \ln(10) = 1.5\times25\text{ mV}\times2.303 = 86.4\text{ mV/decade}.$ Why: Steeper (smaller) $S$ means sharper on/off transition; ideal limit $60\text{ mV/dec}$ at $n=1$ . (3)

(d) In a stack, lower transistors raise the source of upper transistors, giving $V_{SB}>0$ → body effect raises their $V_{th}$ (as in (a), +0.26 V), which reduces subthreshold leakage — this "stack effect" is actively helpful for leakage. Reverse body bias applies $V_{SB}>0$ deliberately in standby to raise $V_{th}$ and exponentially cut leakage, trading some speed for lower static power. (3)

Question 5

(a) NMOS: conduction loss $=I^2 R_{DS(on)} = 2^2\times0.025 = 0.1\text{ W}$ ; gate draws ~zero static current (voltage-controlled). But note $V_{GS}=3.3\text{ V}$ with $V_{th}=1.2\text{ V}$ gives $\sim2.1\text{ V}$ overdrive — usable for logic-level FET. BJT: saturation loss $=V_{CE(sat)}\times I_C = 0.3\times2 = 0.6\text{ W}$ ; base needs $I_B\ge I_C/\beta=2/100=20\text{ mA}$ continuous drive → static drive power + 6× higher conduction loss. Choice: NMOS — 6× lower conduction loss (0.1 W vs 0.6 W) and negligible static drive current → minimum static power. (5)

(b) Both conduct at $V_{GS}=0$ : the JFET channel exists until a reverse gate voltage pinches it off; the depletion-MOSFET has a pre-formed (implanted) channel. Both need a gate voltage to turn off. Circuit consequence: a fault/floating gate leaves them conducting — need pull-off bias; also useful as constant-current source / self-biased load. (3)

(c) Any two: (i) DIBL (drain-induced barrier lowering) — high $V_{DS}$ lowers the barrier, reducing effective $V_{th}$ and raising leakage. (ii) Velocity saturation — carriers hit max drift velocity, current no longer $\propto V_{ov}^2$ . (iii) $V_{th}$ roll-off — short channels have lower $V_{th}$ due to charge sharing. (iv) Punch-through — depletion regions merge, large leakage. (2)

[
  {"claim":"Q1a saturated Ic = 98.3 mA","code":"Ic=(12-0.2)/120; result=abs(Ic-0.09833)<1e-4"},
  {"claim":"Q1c minimum RB before rounding ~508 ohm","code":"Ib=3*( (12-0.2)/120 )/60; RB=(3.3-0.8)/Ib; result=abs(RB-508)<3"},
  {"claim":"Q3a Id saturation = 0.36 mA","code":"Id=Rational(1,2)*Rational(1,2)*(2.0-0.8)**2; result=abs(float(Id)-0.36)<1e-6"},
  {"claim":"Q3d triode Id ~2.47 mA","code":"x=symbols('x'); sol=solve(Eq((10-x)/3,0.5*(3.2*x-0.5*x**2)),x); vals=[float(s) for s in sol if float(s)>0 and float(s)<3.2]; Idt=(10-vals[0])/3; result=abs(Idt-2.47)<0.05"},
  {"claim":"Q4a Vth with body effect = 0.758 V","code":"import sympy as sp; Vth=0.5+0.4*(sp.sqrt(2.2)-sp.sqrt(0.7)); result=abs(float(Vth)-0.758)<1e-3"},
  {"claim":"Q4c subthreshold swing = 86.4 mV/dec","code":"import sympy as sp; S=1.5*25*float(sp.log(10)); result=abs(S-86.