⏱ 45 minutes60 marksprintable — key stays hidden on paper
Level 3 — Production (from-scratch derivations, code-from-memory, explain-out-loud)Time limit: 45 minutes
Total marks: 60
Instructions: Show all working. Where derivations are requested, start from stated device equations. Constants may be left symbolic unless numbers are given.
Question 1 — BJT switch design from scratch (10 marks)
An NPN BJT drives a relay coil. Supply VCC=12 V, collector load resistance RC=120Ω, transistor βmin=50, VCE(sat)=0.2 V, VBE(on)=0.7 V. Driving logic level is 5 V.
(a) Derive the collector saturation current IC(sat). (2)
(b) Compute the minimum base current for hard saturation and choose a base resistor RB using an overdrive factor of 3. (5)
(c) Explain out loud (2–3 sentences) why an overdrive factor > 1 is used in switching design. (3)
(a) Starting from the KCL relation IE=IC+IB and the definitions α=IC/IE, β=IC/IB, derive β=1−αα and α=1+ββ. (5)
(b) A transistor has α=0.995. Compute β. Then state how much β changes if α drops to 0.990, and comment on sensitivity. (3)
For an NMOS in saturation, ID=21knLW(VGS−Vth)2 where kn=μnCox.
(a) Derive the small-signal transconductance gm=∂ID/∂VGS and show it equals 2knLWID. (5)
(b) Given knLW=2 mA/V2, Vth=0.8 V, VGS=2.0 V, compute ID and gm. (4)
(c) Explain why, for a fixed ID, increasing W/L increases gm, and give one design cost of doing so. (3)
A CE amplifier: VCC=10 V, RC=2 kΩ, RE=500Ω (bypassed for AC), voltage-divider bias R1=47 kΩ, R2=10 kΩ, β=150, VBE=0.7 V.
(a) Compute the DC base (Thevenin) voltage and the emitter/collector currents. (5)
(b) Compute gm=IC/VT (use VT=25 mV) and the small-signal midband voltage gain Av=−gmRC. (4)
(c) Explain out loud why bypassing RE increases gain but worsens bias stability of the AC operating point in one respect. (3)
Question 5 — MOSFET regions & subthreshold, code-from-memory (10 marks)
(a) State the three operating conditions (cutoff, triode, saturation) of an NMOS in terms of VGS, Vth, and VDS. (3)
(b) Write, from memory, a short function (pseudocode or Python) id_nmos(vgs, vds, vth, k) returning drain current using the ideal square-law model, correctly selecting region. (4)
(c) Explain what subthreshold leakage is and why it worsens as Vth is scaled down. (3)
Question 6 — Body effect (8 marks)
The threshold with body bias is Vth=Vth0+γ(2ϕF+VSB−2ϕF).
(a) Given Vth0=0.5 V, γ=0.4V1/2, 2ϕF=0.7 V, VSB=1.5 V, compute Vth. (4)
(b) Explain physically why a positive VSB raises Vth in an NMOS. (4)
(a) In saturation the collector is nearly grounded:
IC(sat)=RCVCC−VCE(sat)=12012−0.2=12011.8=0.0983 A≈98.3 mA.(Setup of loop 1 mark, value 1 mark.)
(b) Minimum base current: IB(min)=IC(sat)/βmin=0.0983/50=1.967 mA. (2)
With overdrive factor 3: IB=3×1.967=5.90 mA. (1)RB=IBVlogic−VBE=5.90×10−35−0.7=0.005904.3=729Ω.
Choose nearest standard ≈ 680Ω (increases overdrive slightly, safe). (2)
(c) Overdrive (forcing IB above the minimum) guarantees the transistor stays fully saturated despite the lowest possible β (spread across parts/temperature), keeps VCE(sat) low (low power loss), and speeds turn-on. (3, one mark per valid reason.)
(a) From IE=IC+IB, divide by IC: ICIE=1+ICIB. Since α=IC/IE⇒IE/IC=1/α, and β=IC/IB⇒IB/IC=1/β:
α1=1+β1⇒β1=α1−α⇒β=1−αα.(3)
Invert: β(1−α)=α⇒β=α(1+β)⇒α=1+ββ.(2)
(b)β=0.0050.995=199. (1)
At α=0.990: β=0.0100.990=99. (1) A 0.5% change in α roughly halves β (199→99) — β is extremely sensitive to α near unity. (1)
(c) For fixed ID, gm=2kn(W/L)ID rises with W/L; larger device means larger current at same Vov (or lower Vov), giving more gain. Cost: larger gate capacitance / area → lower bandwidth and more power/chip area. (3)
(a) Thevenin: VTH=VCCR1+R2R2=10⋅5710=1.754 V. (2)RTH=R1∥R2=5747⋅10=8.246 kΩ.
IE≈RE+RTH/βVTH−VBE=500+8246/1501.754−0.7=500+54.971.054=554.971.054=1.899 mA.(2)IC≈IE=1.90 mA (or ≈1.90 mA neglecting RTH/β: 1.054/500=2.11 mA acceptable if stated). (1)
(c) Bypassing RE removes AC negative feedback so full gmRC gain appears (large gain). But without AC feedback the gain now depends directly on gm (hence IC), which varies with temperature and β; so the AC gain becomes far more sensitive to bias-point drift than the emitter-degenerated case. (3)
(b)(4: correct region logic 2, correct equations 2)
def id_nmos(vgs, vds, vth, k): # k = kn*(W/L) vov = vgs - vth if vov <= 0: return 0.0 # cutoff if vds < vov: return k * (vov*vds - 0.5*vds**2) # triode return 0.5 * k * vov**2 # saturation
(c) Subthreshold leakage is the small drain current that flows when VGS<Vth (weak inversion), varying exponentially with VGS. Lowering Vth shifts that exponential curve so more current flows at VGS=0, so off-state leakage rises exponentially as Vth is scaled down. (3)
(b) A positive VSB reverse-biases the source–body junction, widening the depletion region under the channel. More depletion charge must be supported by the gate before inversion occurs, so a larger VGS (higher Vth) is needed to form the channel. (4)
[ {"claim":"Q1a Ic_sat = 98.3 mA", "code":"Ic=(12-0.2)/120; result = abs(Ic-0.09833)<1e-4"}, {"claim":"Q1b RB ~ 729 ohm at overdrive 3", "code":"Ib=3*((12-0.2)/120)/50; RB=(5-0.7)/Ib; result = abs(RB-729)<5"}, {"claim":"Q2b beta=199 at alpha=0.995", "code":"a=Rational(995,1000); b=a/(1-a); result = b==199"}, {"claim":"Q3b Id=1.44mA and gm=2.4mS", "code":"Id=Rational(1,2)*2e-3*(1.2)**2; gm=2e-3*1.2; result = abs(Id-1.44e-3)<1e-9 and abs(gm-2.4e-3)<1e-9"}, {"claim":"Q3a gm equals sqrt(2k*Id)", "code":"k=2e-3; Id=1.44e-3; gm1=k*1.2; gm2=sqrt(2*k*Id); result = abs(float(gm1-gm2))<1e-9"}, {"claim":"Q6a Vth ~ 0.7586 V", "code":"Vth=0.5+0.4*(sqrt(2.2)-sqrt(0.7)); result = abs(float(Vth)-0.7586)<1e-3"}]