Interleaved — Phase 5

Hardware interleaved practice

printable — key stays hidden on paper

ISA & Pipelining Mixed Drill

Instructions: Work each problem independently. Each mixes a different subtopic — decide the method/model before computing. Show work. Assume RV32I unless stated. Total: 60 marks.

1. (6 marks) A byte sequence at address 0x1000 is 0x12 0x34 0x56 0x78 (in ascending address order). A 32-bit load word reads it as a single integer. Give the resulting hex value under little-endian and under big-endian. Then state which one x86 uses and which one is the RISC-V default.

2. (6 marks) Consider this RV32I sequence:

lw   x5, 0(x10)
add  x6, x5, x7
sub  x8, x6, x9

On a classic 5-stage pipeline with full forwarding, identify every hazard by type and state exactly how many stall cycles (bubbles) are required, and why forwarding alone cannot remove all of them.

3. (6 marks) Encode the instruction addi x5, x6, -20 in RV32I. Give the field breakdown (opcode, funct3, rs1, rd, imm) and the final 32-bit binary. State which instruction format this uses and why the immediate is that width.

4. (6 marks) A processor runs a program of $10^6$ instructions. Composition: 25% loads, 10% branches, 65% ALU. Base CPI = 1. Each load incurs an average 0.4 extra cycles (load-use), each branch incurs 1.5 extra cycles (misprediction penalty). Compute the effective CPI and the total cycle count.

5. (6 marks) Classify each addressing mode used and give an equivalent effective-address expression: (a) lw x5, 8(x2) (b) x86 mov eax, [ebx + esi*4 + 16] (c) la x5, symbol (pseudo, PC-relative).

6. (6 marks) Explain the load/store architecture constraint. Then rewrite the following (illegal-looking) pseudo-operation mem[A] = mem[A] + mem[B] as a legal RISC-V instruction sequence, assuming addresses of A and B are in x10 and x11.

7. (6 marks) A designer proposes moving from a 5-stage pipeline to a 15-stage pipeline. Clock frequency rises from 1.0 GHz to 2.2 GHz. Branch misprediction penalty rises from 2 cycles to 10 cycles, and mispredictions occur on 4% of all instructions. Assuming otherwise CPI=1 (ideal) plus branch penalties, compute the instruction throughput (instructions/sec) for both designs and state which wins.

8. (6 marks) Under the RISC-V calling convention (RV32I ABI): which registers are caller-saved vs callee-saved for t0, s1, a0, ra? Where does the return address go, and where is the first integer argument and integer return value?

9. (6 marks) A CPU without forwarding uses a hazard detection unit that stalls on RAW dependencies. For the sequence below, count stall cycles with (a) no forwarding, stall-only, and (b) full forwarding:

add  x1, x2, x3
or   x4, x1, x5
and  x6, x1, x4

10. (6 marks) Match each RISC-V extension letter to its function and give one representative instruction: M, A, F, C. Then explain why an atomic (A) instruction cannot be decomposed into a plain load + store in a load/store ISA and still be correct.

Answer keyMark scheme & solutions

1. (Endianness — 5.1.11) Bytes ascending: addr 0x1000=0x12, 0x1001=0x34, 0x1002=0x56, 0x1003=0x78.

Little-endian: lowest address = least-significant byte → value = 0x78563412.
Big-endian: lowest address = most-significant byte → value = 0x12345678.
x86 is little-endian; RISC-V default is little-endian (bi-endian capable but LE default). Why this method: endianness only affects byte ordering within a word, so map addresses→byte significance.

2. (Data/load-use hazard + forwarding — 5.2.6 / 5.2.7)

add depends on x5 from lw → load-use hazard. Forwarding can't help because the load result is only available after MEM, one stage too late → 1 stall bubble.
sub depends on x6 from add → RAW data hazard, fully resolved by EX→EX forwarding → 0 stalls. Total = 1 stall cycle. Forwarding fails on load-use because data isn't ready until end of MEM, but the dependent EX needs it in the same cycle.

3. (Instruction encoding — 5.1.2) addi x5, x6, -20 — I-type.

opcode = 0010011, funct3 = 000, rd = x5 = 00101, rs1 = x6 = 00110.
imm = -20 = 12-bit two's complement = 111111101100. Layout [imm(12) | rs1(5) | funct3(3) | rd(5) | opcode(7)]: 111111101100 00110 000 00101 0010011 = 1111 1110 1100 0011 0000 0010 1001 0011 = 0xFEC30293. Why I-type: immediate arithmetic → 12-bit sign-extended immediate; that's the widest immediate that fits alongside two 5-bit reg fields + funct3 + opcode in 32 bits.

4. (CPI/throughput — 5.2.9) Extra CPI = $0.25(0.4) + 0.10(1.5) + 0.65(0) = 0.10 + 0.15 = 0.25$ . Effective CPI = $1 + 0.25 = 1.25$ . Total cycles = $1.25 \times 10^6 = 1{,}250{,}000$ .

5. (Addressing modes — 5.1.3) (a) Base+displacement (register indirect w/ offset): EA = x2 + 8. (b) Scaled-index base+displacement: EA = ebx + esi*4 + 16. (c) PC-relative: EA = PC + offset (via auipc+addi). Why: each syntax reveals its mode by which components (base, index, scale, disp, PC) appear.

6. (Load/store model — 5.1.9) Load/store ISAs allow memory access only via load/store; ALU ops work on registers.

lw   x12, 0(x10)   # x12 = mem[A]
lw   x13, 0(x11)   # x13 = mem[B]
add  x12, x12, x13 # register-register ALU
sw   x12, 0(x10)   # mem[A] = result

7. (Deep pipelining trade-off — 5.2.11)

5-stage: CPI = $1 + 0.04\times2 = 1.08$ ; throughput = $10^9 / 1.08 = 9.26\times10^8$ IPS.
15-stage: CPI = $1 + 0.04\times10 = 1.40$ ; throughput = $2.2\times10^9 / 1.40 = 1.571\times10^9$ IPS. 15-stage wins (~1.7× higher throughput) — frequency gain outweighs deeper misprediction penalty here.

8. (Calling convention/ABI — 5.1.10)

t0 = temporary → caller-saved. s1 = saved → callee-saved. a0 = argument/return → caller-saved. ra = return address → caller-saved (must be preserved across nested calls by callee if it calls further).
Return address in ra (x1); first integer arg and integer return value both in a0 (x10).

9. (Hazard detection / forwarding — 5.2.10 / 5.2.6)

(a) No forwarding: or needs x1 (written WB by add) → stall until value in reg. With write-in-first-half/read-second-half, or stalls 2 cycles; and also uses x1 but by then it's available via register read → but the dependency chain forces total 2 (some texts count 3 without split-cycle regfile). Using standard split regfile: 2 stalls.
(b) Full forwarding: EX→EX forwarding covers both → 0 stalls.

10. (RISC-V extensions — 5.1.8 / 5.1.9)

M: integer mult/div → mul, div.
A: atomics → lr.w/sc.w, amoadd.w.
F: single-precision float → fadd.s.
C: compressed 16-bit instrs → c.addi. An atomic can't be a plain load+store because between the two, another hart could modify memory — atomicity requires the read-modify-write to be indivisible (hardware lock/LR-SC reservation), which separate instructions cannot guarantee.

[
  {"claim":"addi x5,x6,-20 encodes to 0xFEC30293","code":"imm=(-20)&0xFFF; opcode=0b0010011; funct3=0; rd=5; rs1=6; enc=(imm<<20)|(rs1<<15)|(funct3<<12)|(rd<<7)|opcode; result=(enc==0xFEC30293)"},
  {"claim":"Effective CPI for problem 4 is 1.25 and total cycles 1250000","code":"cpi=1+0.25*0.4+0.10*1.5+0.65*0; cycles=cpi*10**6; result=(abs(cpi-1.25)<1e-9 and abs(cycles-1250000)<1e-6)"},
  {"claim":"15-stage throughput exceeds 5-stage throughput","code":"t5=1e9/(1+0.04*2); t15=2.2e9/(1+0.04*10); result=(t15>t5)"}
]