Hardware interleaved practice

Problem 1 — Subtopic 4.1.4 (DRAM refresh & charge leakage) Why this method: Exponential decay of stored charge ⇒ use $V(t)=V_{dd}e^{-t/\tau}$ and solve for the threshold crossing.

$V(t) = V_{dd}\,e^{-t/\tau},\quad 0.6 = 1.2\,e^{-t/120}$ $e^{-t/120} = 0.5 \Rightarrow t = 120\ln 2 \approx 120(0.6931) = 83.2\text{ ms}$

Answer: $t_{ref} \approx 83.2\text{ ms}$. (Real DRAM refreshes far more often, ~64 ms, for margin.)

Problem 2 — Subtopic 4.1.1 (SRAM 6T structure) The 6T cell uses two cross-coupled inverters (4 transistors: M1–M4) forming a bistable latch; the two access transistors (M5, M6) connect to the bit-lines. The cross-coupled inverters actively drive the stored node — as long as power is applied, the positive feedback loop continuously restores the logic level, so no refresh is needed (it is static). DRAM stores state as charge on a capacitor with a single access transistor; there is no active feedback, so leakage drains the charge and it must be periodically rewritten (dynamic). Fundamental difference: SRAM holds state as a self-sustaining latched state; DRAM holds it as decaying stored charge.

Problem 3 — Subtopic 4.1.10 (MLC/TLC/QLC flash)

• TLC = 3 bits/cell ⇒ $2^3 = \mathbf{8}$ distinct voltage levels.
• QLC = 4 bits/cell ⇒ $2^4 = 16$ levels.
• Factor increase TLC→QLC: $16/8 = \mathbf{2\times}$.

Problem 4 — Subtopic 4.1.14 (bandwidth metrics) + 4.1.6 (DDR) Why this method: Bandwidth = transfers/s × bus width. DDR transfers on both clock edges, so effective transfer rate = $2\times$ clock.

$\text{transfers/s} = 2 \times 1600\times10^6 = 3.2\times10^9$ $\text{width} = 64\text{ bits} = 8\text{ bytes}$ $BW = 3.2\times10^9 \times 8 = 25.6\times10^9\text{ B/s} = \mathbf{25.6\ GB/s}$

The DDR factor of 2 appears because data is latched on both rising and falling clock edges (double data rate).

Problem 5 — Subtopic 4.2.9 (LVS) contrasted with 4.2.8 (DRC) The connectivity check is LVS (Layout vs Schematic) — it extracts a netlist from the drawn layout and compares device/net topology against the schematic netlist to confirm they are electrically identical. This contrasts with DRC (Design Rule Checking), which is purely geometric: it verifies the layout obeys the foundry's minimum width, spacing, enclosure, and density rules — regardless of connectivity.

Problem 6 — Subtopic 4.1.15 (ECC / Hamming) Need $2^p \ge m + p + 1$ with $m = 8$:

• $p=3$: $2^3=8 \ge 8+3+1=12$? No.
• $p=4$: $2^4=16 \ge 8+4+1=13$? Yes.

Answer: $p = 4$ parity bits, total codeword length $= 8 + 4 = \mathbf{12}$ bits (SEC Hamming(12,8)).

Problem 7 — Subtopic 4.1.11 (wear leveling) + 4.1.9 (floating gate) Wear leveling distributes program/erase (P/E) cycles evenly across all flash blocks so no single block wears out prematurely. It's needed because flash erases by tunneling charge off the floating gate (Fowler-Nordheim tunneling), and repeated high-field tunneling gradually damages the oxide, giving each cell a finite endurance (~$10^3$–$10^5$ cycles). SRAM/DRAM store state as latch state or capacitor charge with no destructive physical wear per write, so they need no wear leveling. The floating gate's oxide degradation is the root cause of the limitation.

Problem 8 — Subtopic 4.2.2 (Dennard) vs 4.2.1 (Moore) Dennard scaling: as transistors shrink, voltage and current scale down proportionally so that power density stays constant — allowing higher clock frequencies at the same power/area. Breakdown (~2005): supply voltage $V_{dd}$ stopped scaling down (threshold voltage and leakage/subthreshold currents set a floor), so shrinking transistors no longer kept power density constant → power density rose, ending free frequency scaling and forcing multicore designs. This differs from Moore's Law (transistor count per chip doubling every ~2 years), which continued via miniaturization even after Dennard scaling failed — we kept getting more transistors, just couldn't clock them all faster within the power budget.

Problem 9 — Subtopic 4.1.13 (CAM) In a CAM, you supply a data word (search key) and the hardware compares it against all stored entries in parallel in one cycle, returning the address(es) that match — this is the inverse of RAM. In conventional RAM, you supply an address and it returns the data at that location. Hardware cost: each CAM cell contains extra comparison logic (match transistors + a match/word-line), making CAM significantly larger, more power-hungry, and more expensive per bit than RAM. (Used for TLB/cache tag lookup, network routing tables.)

Problem 10 — Subtopic 4.1.8 (NOR vs NAND flash) (a) Random read / execute-in-place: NOR wins. Cells are connected in parallel to bit-lines allowing fast random byte-level reads, so code can be executed directly from NOR. (b) Density / cost per bit: NAND wins. Cells are in series strings sharing contacts, giving much higher density and lower cost/bit, but only page/block-level (not random-byte) access — ideal for mass storage (SSDs, memory cards).

[
  {
    "claim": "DRAM refresh interval = 120*ln2 ≈ 83.18 ms",
    "code": "import math\nt = 120*math.log(2)\nresult = abs(t - 83.18) < 0.1"
  },
  {
    "claim": "DDR4-1600 (64-bit) peak bandwidth = 25.6 GB/s",
    "code": "clk = 1600e6\ntransfers = 2*clk\nbw = transfers*8/1e9\nresult = abs(bw - 25.6) < 1e-6"
  },
  {
    "claim": "Hamming SEC for 8 data bits needs 4 parity bits, codeword length 12",
    "code": "m=8\np=0\nwhile 2**p < m+p+1:\n    p+=1\nresult = (p==4) and (m+p==12)"
  }
]