Interleaved — Phase 3

Hardware interleaved practice

printable — key stays hidden on paper

Instructions: Solve all problems. Each targets a different subtopic — read carefully and choose the correct method before computing. Show all steps. Marks in brackets. Use $...$ for math notation where helpful.

1. [3 marks] Convert the unsigned decimal number $217$ to (a) 8-bit binary, (b) hexadecimal, and (c) octal.

2. [4 marks] An 8-bit register holds the two's complement pattern $1101\,0110$ . State the signed decimal value it represents, then compute the two's complement representation of its negation and give it in hex.

3. [4 marks] Simplify the 3-variable function using a Karnaugh map: $F(A,B,C) = \sum m(0,1,2,3,6,7)$ Give the minimal SOP expression.

4. [3 marks] Using De Morgan's theorems, express $\overline{A + B\cdot C}$ as a product/sum of complemented literals (fully expanded to individual complemented variables where possible).

5. [4 marks] A CMOS gate has a pull-down network of two NMOS transistors in parallel and a pull-up network of two PMOS transistors in series. Identify the logic function it implements and draw/describe the transistor arrangement. State whether this is NAND or NOR.

6. [4 marks] Build the complete truth table for $Y = (A \oplus B) \cdot \overline{C}$ and identify for how many of the 8 input combinations $Y=1$ .

7. [3 marks] A logic path consists of four gates in series with propagation delays $t_{p1}=2.1\text{ ns}$ , $t_{p2}=1.4\text{ ns}$ , $t_{p3}=3.0\text{ ns}$ , $t_{p4}=1.8\text{ ns}$ . Find the total worst-case propagation delay and the maximum clock frequency (assuming the path is the critical path with no other overhead).

8. [5 marks] Implement $F = \overline{A}\cdot B + A \cdot \overline{B}$ using only 2-input NAND gates. State how many NAND gates you use and justify NAND's universality argument in one line.

9. [4 marks] For an inverter with $V_{DD}=3.3\text{ V}$ , the VTC gives $V_{OH}=3.3$ , $V_{OL}=0$ , $V_{IH}=1.9$ , $V_{IL}=1.3$ V. Compute the noise margins $NM_H$ and $NM_L$ and state which is the weaker margin.

10. [4 marks] Use the Quine–McCluskey method to find the minimal SOP for $F(A,B,C) = \sum m(0,1,2,5,6,7).$ Show the prime implicants.

11. [3 marks] A K-map function has minterms $\sum m(1,3,7)$ with don't-cares $d(0,2,5)$ . Using the don't-cares advantageously, give the simplest SOP expression.

Total: 41 marks

Answer keyMark scheme & solutions

1. (Subtopic 3.1.1 / 3.1.2 — base conversion) $217_{10}$ :

Binary: $217 = 128+64+16+8+1 = 11011001_2$ .
Hex: group nibbles $1101\,1001 = \mathrm{D9}_{16}$ .
Octal: group in 3s from right $011\,011\,001 = 331_8$ . Answers: (a) $11011001$ , (b) $\mathrm{D9}$ , (c) $331$ . Why this method: recognise base-conversion request; nibble grouping for hex, 3-bit grouping for octal.

2. (Subtopic 3.1.3 — two's complement) $1101\,0110$ : MSB=1 → negative. Invert: $0010\,1001$ , add 1: $0010\,1010 = 42$ . So value $= -42$ . Negation $= +42 = 0010\,1010_2 = \mathrm{2A}_{16}$ . Answer: original $=-42$ ; negation $=+42 = \mathrm{2A}_{16}$ . Why: MSB-set signals two's complement decoding, not plain binary.

3. (Subtopic 3.1.11 — K-map) Minterms $0,1,2,3,6,7$ . Map (A rows, BC cols):

$m0,m1,m2,m3$ → $\overline A$ (all A=0) — one quad.
$m2,m3,m6,m7$ → $B$ (B=1 group: minterms with B=1 are 2,3,6,7). Cover: $\overline A + B$ . Answer: $F = \overline{A} + B$ . Why: six adjacent minterms → group into two quads; K-map over algebra for speed.

4. (Subtopic 3.1.8 — De Morgan) $\overline{A + BC} = \overline A \cdot \overline{BC} = \overline A \cdot (\overline B + \overline C)$ . Answer: $\overline{A}\,(\overline B + \overline C)$ . Why: outer NOR → De Morgan to product; inner AND-complement → De Morgan again to a sum.

5. (Subtopic 3.2.3 / 3.2.2 — CMOS gate design) PDN = 2 NMOS in parallel, PUN = 2 PMOS in series. Parallel NMOS conduct if either input high → output pulled low when A OR B is 1. Series PMOS conduct only when both inputs low. This is $\overline{A+B}$ → NOR gate. Answer: 2-input CMOS NOR. Why: PDN topology (parallel = OR-of-conditions) directly dictates the function complement; parallel-NMOS = NOR.

6. (Subtopic 3.1.5 / 3.1.6 — truth table with XOR)

A	B	C	A⊕B	¬C	Y
0	0	0	0	1	0
0	0	1	0	0	0
0	1	0	1	1	1
0	1	1	1	0	0
1	0	0	1	1	1
1	0	1	1	0	0
1	1	0	0	1	0
1	1	1	0	0	0

Answer: $Y=1$ for 2 combinations (rows ABC=010 and 100). Why: systematic truth table; XOR=1 only when A≠B, then gated by ¬C.

7. (Subtopic 3.1.15 / 3.2.7 — propagation delay) Series delays add: $t_{total}=2.1+1.4+3.0+1.8=8.3\text{ ns}$ . $f_{max}=1/8.3\text{ ns} \approx 120.5\text{ MHz}$ . Answer: $8.3$ ns; $\approx 120$ MHz. Why: series gates → sum of delays (not max); frequency = reciprocal of critical path.

8. (Subtopic 3.1.14 — universal gates / NAND) $F=\overline A B + A\overline B = A\oplus B$ . XOR from 4 NANDs: Let $g_1=\overline{AB}$ ; $g_2=\overline{A g_1}$ ; $g_3=\overline{B g_1}$ ; $F=\overline{g_2 g_3}$ . Answer: 4 NAND gates. NAND is functionally complete because it can realise NOT ( $\overline{A\cdot A}$ ), AND, and OR — hence any Boolean function. Why: recognise expression as XOR; standard 4-NAND XOR construction.

9. (Subtopic 3.2.6 — noise margins) $NM_H = V_{OH}-V_{IH}=3.3-1.9=1.4\text{ V}$ . $NM_L = V_{IL}-V_{OL}=1.3-0=1.3\text{ V}$ . Answer: $NM_H=1.4$ V, $NM_L=1.3$ V; $NM_L$ is weaker. Why: apply margin definitions; smaller margin limits noise immunity.

10. (Subtopic 3.1.13 — Quine–McCluskey) Minterms (ABC): 0=000,1=001,2=010,5=101,6=110,7=111. Group by 1-count:

0: 000
1: 001,010 (and... 1-bit: 001,010,100→ only 001,010 present)
2: 101,110
3: 111

Combine adjacents:

000–001 → 00– ( $\overline A\overline B$ )
000–010 → 0–0 ( $\overline A\overline C$ )
001–101 → –01 ( $\overline B C$ )
010–110 → –10 ( $B\overline C$ )
101–111 → 1–1 ( $AC$ )
110–111 → 11– ( $AB$ )

Prime implicants: $\overline A\overline B,\ \overline A\overline C,\ \overline B C,\ B\overline C,\ AC,\ AB$ . Essential coverage — minterm 2 covered only by $\overline A\overline C$ & $B\overline C$ ; select to cover all. A minimal cover: $\overline A\overline B + B\overline C + AC$ (covers 0,1 / 2,6 / 5,7). Check 0(✓ĀB̄),1(✓ĀB̄),2(✓BC̄),5(✓AC),6(✓BC̄),7(✓AC). ✓ Answer: $F = \overline A\,\overline B + B\,\overline C + A C$ . Why: systematic QM tabulation when confirming K-map result / more variables.

11. (Subtopic 3.1.12 — don't-cares) Required 1,3,7; don't-cares 0,2,5. Use $m1,m3$ with dc $m0,m2$ → quad $\overline A$ (minterms 0,1,2,3). Use $m7$ with dc $m5$ → $AC$ (5,7). Answer: $F = \overline A + A C$ , which simplifies to $\overline A + C$ . Why: absorb don't-cares to enlarge groups; verify $\overline A + AC=\overline A + C$ by absorption.

[
  {"claim":"217 = 0xD9 and 0o331 and binary 11011001","code":"result = (217==0xD9) and (217==0o331) and (217==0b11011001)"},
  {"claim":"Two's complement 11010110 as signed 8-bit = -42","code":"v=0b11010110; result = (v-256 if v>=128 else v)==-42"},
  {"claim":"QM result A'B'+BC'+AC equals sum m(0,1,2,5,6,7)","code":"mins=set()\nfor A in range(2):\n for B in range(2):\n  for C in range(2):\n   F=((1-A)and(1-B)) or (B and (1-C)) or (A and C)\n   if F: mins.add(A*4+B*2+C)\nresult = mins=={0,1,2,5,6,7}"}
]