GPU Architecture
Chapter: 6.2 GPU Architecture Difficulty: Level 1 — Recognition (MCQ, Matching, True/False with justification) Time Limit: 20 minutes Total Marks: 40
Section A — Multiple Choice (1 mark each, 10 marks)
Choose the single best answer.
Q1. The core design philosophy that distinguishes a GPU from a CPU is that a GPU is optimized for:
- (a) Minimizing latency of a single thread
- (b) Maximizing throughput across many threads
- (c) Deep branch prediction on serial code
- (d) Large per-core out-of-order execution windows
Q2. In NVIDIA terminology, the group of threads that execute a single instruction in lockstep is called a:
- (a) Block
- (b) Grid
- (c) Warp
- (d) Kernel
Q3. The standard warp size on NVIDIA GPUs is:
- (a) 8 threads
- (b) 16 threads
- (c) 32 threads
- (d) 64 threads
Q4. SIMT stands for:
- (a) Single Instruction Multiple Transistor
- (b) Single Instruction Multiple Thread
- (c) Serial Instruction Multi-Threading
- (d) Shared Instruction Memory Transfer
Q5. Which memory type in the GPU hierarchy has the lowest latency?
- (a) Global memory
- (b) Shared memory
- (c) Registers
- (d) Constant memory
Q6. Coalesced memory access refers to:
- (a) Threads in a warp accessing contiguous/aligned global memory addresses in one transaction
- (b) Combining two kernels into one launch
- (c) Merging shared-memory banks
- (d) Reducing the number of registers per thread
Q7. A bank conflict occurs in shared memory when:
- (a) Two blocks access the same global address
- (b) Multiple threads in a warp access different addresses mapping to the same bank
- (c) The L2 cache is full
- (d) A warp diverges on an if-statement
Q8. Occupancy is best described as:
- (a) The fraction of global memory currently in use
- (b) The ratio of active warps to the maximum warps supported per SM
- (c) The number of kernels running on the GPU
- (d) The clock frequency of the SM
Q9. Warp divergence penalties arise primarily from:
- (a) Coalesced loads
- (b) Threads within a warp taking different branch paths, forcing serialized execution
- (c) Too many registers
- (d) Using shared memory
Q10. Tensor cores are specialized hardware units designed to accelerate:
- (a) Integer sorting
- (b) Matrix multiply-accumulate (MMA) operations
- (c) Branch prediction
- (d) Texture filtering only
Section B — Matching (1 mark each, 10 marks)
Match each term in Column X to its correct description in Column Y. Write pairs like Q11 → C.
| # | Column X |
|---|---|
| Q11 | Streaming Multiprocessor (SM) |
| Q12 | CUDA core |
| Q13 | Thread block |
| Q14 | Grid |
| Q15 | Global memory |
| Q16 | Shared memory |
| Q17 | Registers |
| Q18 | Warp scheduler |
| Q19 | ROCm |
| Q20 | Latency hiding |
| Letter | Column Y |
|---|---|
| A | On-chip memory shared by threads of a block; user-managed scratchpad |
| B | AMD's open GPU compute platform / CUDA alternative |
| C | The processing unit that executes threads and contains CUDA cores, schedulers, and shared memory |
| D | A collection of thread blocks launched by a kernel |
| E | Selects which ready warp to issue each cycle to keep execution units busy |
| F | Fastest, per-thread private storage |
| G | Group of threads that can cooperate and share on-chip memory |
| H | Large, high-latency off-chip DRAM accessible by all threads |
| I | Overlapping stalled warps with ready warps to keep the SM busy |
| J | A scalar arithmetic execution lane inside an SM |
Section C — True/False with Justification (2 marks each, 20 marks)
State True or False (1 mark) and give a one-line justification (1 mark).
Q21. Increasing occupancy always guarantees higher kernel performance.
Q22. All threads in a single warp share the same program counter under classic SIMT execution.
Q23. Accessing global memory has lower latency than accessing shared memory.
Q24. A grid can contain multiple thread blocks, and blocks can be scheduled independently across SMs.
Q25. Bank conflicts affect global memory transactions, not shared memory.
Q26. GPUs devote a larger fraction of die area to arithmetic units (ALUs) than CPUs do.
Q27. Warp divergence has no performance cost as long as the code compiles.
Q28. OpenCL is a vendor-locked API that runs only on NVIDIA hardware.
Q29. Memory coalescing improves effective memory bandwidth by reducing the number of memory transactions per warp.
Q30. Tensor cores compute a full FP32 matrix product but cannot accumulate results.
Answer keyMark scheme & solutions
Section A (10 marks)
| Q | Ans | Why (1 mark each) |
|---|---|---|
| Q1 | (b) | GPUs are throughput machines using massive parallelism; CPUs minimize single-thread latency. |
| Q2 | (c) | A warp is the SIMT execution group issued one instruction at a time. |
| Q3 | (c) | NVIDIA warps = 32 threads. |
| Q4 | (b) | Single Instruction, Multiple Thread — the NVIDIA execution model. |
| Q5 | (c) | Registers are on-chip, per-thread, lowest latency (~1 cycle). |
| Q6 | (a) | Coalescing = warp threads hit contiguous/aligned addresses served in fewest transactions. |
| Q7 | (b) | Shared memory is banked; same-bank simultaneous accesses serialize. |
| Q8 | (b) | Occupancy = active warps ÷ max warps per SM. |
| Q9 | (b) | Divergent branches serialize execution of the differing paths. |
| Q10 | (b) | Tensor cores accelerate matrix multiply-accumulate (D = A·B + C). |
Section B (10 marks)
| Q | Match | Reason |
|---|---|---|
| Q11 | C | SM = the core processing block. |
| Q12 | J | CUDA core = scalar ALU lane. |
| Q13 | G | Block = cooperating threads sharing shared memory. |
| Q14 | D | Grid = set of blocks per kernel. |
| Q15 | H | Global = off-chip DRAM, all threads. |
| Q16 | A | Shared = on-chip block scratchpad. |
| Q17 | F | Registers = fastest private storage. |
| Q18 | E | Warp scheduler issues ready warps. |
| Q19 | B | ROCm = AMD compute platform. |
| Q20 | I | Latency hiding overlaps stalls with ready warps. |
Section C (20 marks)
Q21. False — Higher occupancy helps hide latency but performance can be bound by memory bandwidth, register pressure, or divergence; beyond a point it does not help. (1+1)
Q22. True — In classic (pre-Volta) SIMT, a warp shares one PC; all threads execute the same instruction together. (1+1)
Q23. False — Global memory (off-chip DRAM) has much higher latency than on-chip shared memory. (1+1)
Q24. True — A grid holds many blocks; blocks are independent and distributed across SMs by the scheduler. (1+1)
Q25. False — Bank conflicts are a shared-memory phenomenon; global memory has coalescing, not banks. (1+1)
Q26. True — GPUs allocate more transistors to ALUs and fewer to control/cache versus CPUs. (1+1)
Q27. False — Divergence serializes the taken paths within a warp, wasting cycles/lanes. (1+1)
Q28. False — OpenCL is an open, cross-vendor standard (runs on NVIDIA, AMD, Intel, etc.). (1+1)
Q29. True — Coalescing groups warp accesses into fewer, wider transactions, raising effective bandwidth. (1+1)
Q30. False — Tensor cores perform multiply-accumulate (D = A·B + C); accumulation is intrinsic. (1+1)
Illustrative numeric checks (referenced by verify block)
- Warp size = 32 (Q3).
- Occupancy example: if 48 active warps of 64 max → occupancy = 48/64 = 0.75.
- Coalescing: 32 threads each reading 4 bytes contiguous = 128 bytes = one 128-byte transaction (1 transaction) vs 32 scattered transactions.
[
{"claim":"Warp size is 32","code":"warp=32\nresult = (warp==32)"},
{"claim":"Occupancy 48/64 active warps equals 0.75","code":"occ = Rational(48,64)\nresult = (occ == Rational(3,4))"},
{"claim":"32 threads x 4 bytes coalesce into a single 128-byte transaction","code":"total = 32*4\ntx = total/128\nresult = (total==128 and tx==1)"},
{"claim":"Scattered access needs up to 32 transactions vs 1 coalesced (32x more)","code":"result = (32/1 == 32)"}
]