Level 4 — ApplicationDiodes & Applications

Diodes & Applications

60 minutes60 marksprintable — key stays hidden on paper

Level: 4 — Application (novel problems, no hints) Time limit: 60 minutes Total marks: 60

Assume silicon diode forward drop VF=0.7 VV_F = 0.7\text{ V} and Schottky VF=0.3 VV_F = 0.3\text{ V} unless a datasheet value is given. Use ideal diodes only where explicitly stated.


Question 1 — Rectifier + Filter Design (14 marks)

A designer needs a DC supply that delivers Iload=250 mAI_{load} = 250\text{ mA} with a maximum peak-to-peak ripple of 0.5 V0.5\text{ V}. The mains transformer secondary provides 12 Vrms12\text{ V}_{rms} at 50 Hz50\text{ Hz}. A full-wave bridge rectifier feeds a smoothing capacitor.

(a) Calculate the peak voltage across the load after the bridge (account for the two conducting silicon diodes). (3)

(b) Derive the required smoothing capacitance CC using the approximation Vripple(pp)IloadfrippleCV_{ripple(pp)} \approx \dfrac{I_{load}}{f_{ripple}\,C}. State the ripple frequency you use and justify it. (5)

(c) The same specification is now attempted with a half-wave rectifier using the identical capacitor from part (b). What ripple voltage results? Comment on why the full-wave topology was the better engineering choice. (4)

(d) State the minimum Peak Inverse Voltage (PIV) rating each diode in the bridge must withstand. (2)


Question 2 — Zener Regulator Under Varying Load (13 marks)

A 5.1 V5.1\text{ V} Zener diode regulates an unregulated input that varies between 9 V9\text{ V} and 12 V12\text{ V}. A series resistor RSR_S is used. The load current varies between 00 and 40 mA40\text{ mA}. The Zener requires a minimum holding current of 5 mA5\text{ mA} to stay in regulation.

(a) Determine the value of RSR_S that guarantees regulation under the worst-case combination of input voltage and load current. Identify that worst case and justify it. (6)

(b) Using your chosen RSR_S, compute the maximum power dissipated in the Zener diode. Identify the input/load condition that produces it. (5)

(c) State one datasheet parameter (other than VZV_Z) you would check before finalising this Zener choice, and why. (2)


Question 3 — Clipper/Clamper Analysis (12 marks)

An input signal vin(t)=8sin(ωt) Vv_{in}(t) = 8\sin(\omega t)\text{ V} is applied to the circuit below. The diode is ideal (VF=0V_F = 0), and a 2 V2\text{ V} DC battery is in series with the diode; the diode–battery branch is connected from the output node to ground so the diode conducts when the output tries to exceed +2 V+2\text{ V}.

(a) Sketch and describe the output waveform vout(t)v_{out}(t), giving the clipped level and the untouched portion. (4)

(b) Now replace the ideal diode with a silicon diode (VF=0.7 VV_F = 0.7\text{ V}). State the new clipping level and explain the shift. (3)

(c) A DC-restorer (clamper) is instead built with a capacitor in series and the same diode-to-ground (cathode to ground, ideal diode). For the same input, state the output DC level and the peak and trough voltages of voutv_{out} after the clamp settles. (5)


Question 4 — Optoelectronic Component Calculations (11 marks)

(a) A red LED with VF=1.8 VV_F = 1.8\text{ V} is to run at 15 mA15\text{ mA} from a 5 V5\text{ V} rail through a series resistor. Compute the resistor value and the power it dissipates. Choose a standard E12E12 resistor value (\ge your computed value) and state the resulting current. (5)

(b) A silicon solar cell delivers a short-circuit current Isc=120 mAI_{sc} = 120\text{ mA} and open-circuit voltage Voc=0.58 VV_{oc} = 0.58\text{ V}. Its maximum-power point is at Vmp=0.47 VV_{mp}=0.47\text{ V}, Imp=110 mAI_{mp}=110\text{ mA}. Calculate the fill factor and the maximum output power. (4)

(c) Explain why a photodiode is normally operated in reverse bias for light-sensing applications, whereas a solar cell operates in forward-voltage (photovoltaic) mode. (2)


Question 5 — Diode Logic & Datasheet Reasoning (10 marks)

(a) A two-input diode AND gate uses two diodes with anodes tied to inputs A and B and cathodes joined to output YY, with a pull-up resistor from YY to +5 V+5\text{ V}. Using VF=0.7 VV_F = 0.7\text{ V}, complete a truth table of output voltages (not just logic levels) for all four input combinations where a logic-0 input = 0 V0\text{ V} and a logic-1 input = 5 V5\text{ V}. (5)

(b) Explain one reason diode logic cannot be cascaded through many stages, referencing the level degradation you observed in (a). (2)

(c) A varactor diode has a junction capacitance given by Cj=C01+VR/0.7C_j = \dfrac{C_0}{\sqrt{1 + V_R/0.7}} with C0=80 pFC_0 = 80\text{ pF}. Compute CjC_j at VR=0 VV_R = 0\text{ V} and VR=6 VV_R = 6\text{ V}, and state the tuning ratio. (3)


END OF PAPER

Answer keyMark scheme & solutions

Question 1 (14 marks)

(a) Peak secondary voltage Vpk=122=16.97 VV_{pk} = 12\sqrt{2} = 16.97\text{ V}. Bridge has two diodes conducting in series each half-cycle, so Vpeak,load=16.972(0.7)=15.57 VV_{peak,load} = 16.97 - 2(0.7) = 15.57\text{ V}. (3) (1 mark VpkV_{pk}, 1 for subtracting 2 drops, 1 answer)

(b) Ripple frequency for a full-wave/bridge rectifier is 2×2\times mains = 100 Hz100\text{ Hz} (both half-cycles produce output pulses). (1 justify) C=IloadfrippleVripple=0.25100×0.5=5.0×103 F=5000 μF.C = \frac{I_{load}}{f_{ripple}\,V_{ripple}} = \frac{0.25}{100 \times 0.5} = 5.0\times10^{-3}\text{ F} = 5000\ \mu\text{F}. (2 formula rearrange, 2 answer)

(c) Half-wave: ripple frequency = 50 Hz50\text{ Hz} (only one pulse per cycle), so with same CC: Vripple=IloadfC=0.2550×5000×106=1.0 V (pp).V_{ripple} = \frac{I_{load}}{f\,C} = \frac{0.25}{50 \times 5000\times10^{-6}} = 1.0\text{ V (pp)}. This is double the target ripple — the half-wave design fails the 0.5 V0.5\text{ V} spec and would need twice the capacitance. Full-wave charges the cap twice as often, halving ripple for the same CC; hence the better choice. (2 calc, 2 comment)

(d) For a bridge, each diode sees a maximum reverse voltage of one peak = 16.97 V16.97\text{ V} (≈ VpkV_{pk}, since two diodes share the reverse blocking but each blocks Vpk\approx V_{pk}). Minimum PIV rating 17 V\gtrsim 17\text{ V}; choose with margin (e.g. 50 V). (2)


Question 2 (13 marks)

(a) Worst case for keeping the Zener in regulation is minimum input voltage (least available current) and maximum load current (most current diverted from Zener). At Vin=9 VV_{in}=9\text{ V}, IL=40 mAI_L = 40\text{ mA}, the Zener still needs 5 mA\ge 5\text{ mA}. Total current through RSR_S = IL+IZ(min)=40+5=45 mAI_L + I_{Z(min)} = 40 + 5 = 45\text{ mA}. RS=Vin(min)VZIL+IZ,min=95.145×103=3.90.045=86.7 Ω.R_S = \frac{V_{in(min)} - V_Z}{I_L + I_{Z,min}} = \frac{9 - 5.1}{45\times10^{-3}} = \frac{3.9}{0.045} = 86.7\ \Omega. Choose RS86.7 ΩR_S \le 86.7\ \Omega (a smaller value gives more margin); take RS=82 ΩR_S = 82\ \Omega. (2 worst case, 2 formula, 2 answer)

(b) Max Zener power occurs at max input (12 V12\text{ V}) and min load (0 mA0\text{ mA}) — all current flows through the Zener. With RS=82 ΩR_S = 82\ \Omega: IS=125.182=6.982=84.1 mA,IZ=84.1 mA (all).I_{S} = \frac{12 - 5.1}{82} = \frac{6.9}{82} = 84.1\text{ mA}, \quad I_Z = 84.1\text{ mA (all)}. PZ=VZIZ=5.1×0.0841=0.429 W.P_Z = V_Z I_Z = 5.1 \times 0.0841 = 0.429\text{ W}. So a Zener rated 0.5 W\ge 0.5\text{ W} (with margin ~1 W) is required. (1 condition, 2 current, 2 power)

(If RS=86.7 ΩR_S = 86.7\ \Omega used: IZ=79.6 mAI_Z = 79.6\text{ mA}, PZ=0.406 WP_Z = 0.406\text{ W} — accept.)

(c) Any of: max power dissipation PZmaxP_{Zmax} (must exceed 0.43 W); Zener dynamic impedance ZZZ_Z (affects regulation tightness); tolerance on VZV_Z. (2)


Question 3 (12 marks)

(a) Diode conducts when voutv_{out} would exceed +2 V+2\text{ V}, clamping the top. Output = input for vin<2 Vv_{in} < 2\text{ V}, and clipped flat at +2 V+2\text{ V} for the portion where vin>2 Vv_{in} > 2\text{ V}. Negative half-cycle (down to 8 V-8\text{ V}) passes unaltered. This is a positive clipper (limiter) at +2 V+2\text{ V}. (4)

(b) With silicon diode the branch conducts only when node voltage =2+0.7=2.7 V= 2 + 0.7 = 2.7\text{ V}. New clipping level =+2.7 V= +2.7\text{ V}; the 0.7 V0.7\text{ V} forward drop raises the clamp point. (3)

(c) Clamper (cathode to ground, ideal): the diode conducts on the positive peaks, charging the capacitor so the output cannot exceed 0 V0\text{ V}. The waveform is shifted down so its peak sits at 0 V0\text{ V}.

  • Peak: 0 V0\text{ V}
  • Trough: 0(8(8))=16 V0 - (8-(-8)) = -16\text{ V}
  • DC level (average): 8 V-8\text{ V}. (2 peak/trough logic, 2 values, 1 DC level)

Question 4 (11 marks)

(a) R=51.815×103=3.20.015=213.3 Ω.R = \frac{5 - 1.8}{15\times10^{-3}} = \frac{3.2}{0.015} = 213.3\ \Omega. Standard E12213.3 ΩE12 \ge 213.3\ \Omega is 220 Ω220\ \Omega. Resulting current I=3.2220=14.5 mAI = \dfrac{3.2}{220} = 14.5\text{ mA}. Power in resistor P=I2R=(0.01455)2×220=0.0466 W47 mWP = I^2 R = (0.01455)^2 \times 220 = 0.0466\text{ W} \approx 47\text{ mW} (or using computed 1515 mA: P=3.2×0.015=48 mWP=3.2\times0.015=48\text{ mW}). (2 R, 1 std value, 1 current, 1 power)

(b) Fill factor FF=VmpImpVocIsc=0.47×0.1100.58×0.120=0.05170.0696=0.743.FF = \frac{V_{mp} I_{mp}}{V_{oc} I_{sc}} = \frac{0.47 \times 0.110}{0.58 \times 0.120} = \frac{0.0517}{0.0696} = 0.743. Max power Pmax=VmpImp=0.47×0.110=51.7 mWP_{max} = V_{mp} I_{mp} = 0.47 \times 0.110 = 51.7\text{ mW}. (2 FF, 2 Pmax)

(c) Reverse bias widens the depletion region → lower junction capacitance (faster response) and gives a linear, wide photocurrent-vs-illumination response with fast switching for sensing. A solar cell must deliver power, so it operates in the fourth quadrant (forward voltage, reverse current), the photovoltaic mode. (2)


Question 5 (10 marks)

(a) With pull-up to +5 V+5\text{ V}: any input at 0 V0\text{ V} pulls YY down via its diode to 0+0.7=0.7 V0 + 0.7 = 0.7\text{ V}. Only when both inputs are 5 V5\text{ V} do both diodes turn off and YY is pulled to 5 V5\text{ V}.

A (V) B (V) Y (V)
0 0 0.7
0 5 0.7
5 0 0.7
5 5 5.0

This is an AND gate (Y high only when A AND B high). (4 table, 1 identify)

(b) Each diode adds a 0.7 V0.7\text{ V} offset (logic-0 is 0.7 V0.7\text{ V}, not 0 V0\text{ V}; logic-1 loses a drop in OR-type stages). Cascading accumulates these offsets, so after several stages the "0" and "1" levels drift toward each other and the logic margin collapses. Diode logic also cannot restore/amplify levels. (2)

(c) At VR=0V_R = 0: Cj=80/1+0=80 pFC_j = 80/\sqrt{1+0} = 80\text{ pF}. At VR=6V_R = 6: Cj=80/1+6/0.7=80/9.571=80/3.094=25.86 pFC_j = 80/\sqrt{1 + 6/0.7} = 80/\sqrt{9.571} = 80/3.094 = 25.86\text{ pF}. Tuning ratio =80/25.86=3.09:1= 80/25.86 = 3.09:1. (1 + 1 + 1)


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  {"claim":"Bridge peak load voltage = 12*sqrt(2) - 1.4 = 15.57 V","code":"vpk=12*sqrt(2)-2*Rational(7,10); result=abs(float(vpk)-15.57)<0.02"},
  {"claim":"Smoothing C for full-wave = 5000 uF","code":"C=Rational(25,100)/(100*Rational(5,10)); result=abs(float(C)-0.005)<1e-9"},
  {"claim":"Half-wave ripple with same C = 1.0 V","code":"Vr=Rational(25,100)/(50*Rational(5,1000)); result=abs(float(Vr)-1.0)<1e-9"},
  {"claim":"Rs worst case = 86.67 ohm","code":"Rs=(9-Rational(51,10))/(Rational(45,1000)); result=abs(float(Rs)-86.6667)<0.01"},
  {"claim":"Max Zener power with Rs=82 is ~0.429 W","code":"Iz=(12-Rational(51,10))/82; Pz=Rational(51,10)*Iz; result=abs(float(Pz)-0.4293)<0.005"},
  {"claim":"Solar fill factor = 0.743","code":"FF=(Rational(47,100)*Rational(11,100))/(Rational(58,100)*Rational(12,100)); result=abs(float(FF)-0.743)<0.005"},
  {"claim":"Varactor Cj at 6V = 25.86 pF, ratio 3.09","code":"Cj=80/sqrt(1+Rational(6,1)/Rational(7,10)); ratio=80/Cj; result=abs(float(Cj)-25.86)<0.1 and abs(float(ratio)-3.094)<0.02"}
]