Level 3 — ProductionDiodes & Applications

Diodes & Applications

45 minutes60 marksprintable — key stays hidden on paper

Level: 3 — Production (from-scratch derivations, explain-out-loud, design-from-memory) Time limit: 45 minutes Total marks: 60

Instructions: Show all working. Assume silicon diode forward drop Vf=0.7 VV_f = 0.7\text{ V} unless a datasheet value is stated. Treat diodes as ideal (with the stated VfV_f) except where a model is requested.


Question 1 — Half-wave rectifier derivation (10 marks)

A half-wave rectifier drives a purely resistive load RLR_L from a source vin(t)=Vmsin(ωt)v_{in}(t) = V_m\sin(\omega t) through a single silicon diode.

(a) From first principles, derive the expression for the average (DC) output voltage VDCV_{DC} across RLR_L, treating the diode as ideal (Vf=0V_f = 0). Show the integral setup. (4)

(b) Derive the RMS output voltage VrmsV_{rms} for the same ideal case. (3)

(c) Explain out loud, in 2–3 sentences, why the ripple frequency at the output equals the supply frequency for a half-wave rectifier but doubles for a full-wave rectifier. (3)


Question 2 — Bridge rectifier design (10 marks)

You must design a bridge rectifier producing a DC output from a 230 Vrms230\text{ V}_{rms}, 50 Hz50\text{ Hz} mains via a transformer whose secondary is 12 Vrms12\text{ V}_{rms}.

(a) Compute the peak secondary voltage and the peak output voltage across the load (account for the two conducting silicon diodes, Vf=0.7 VV_f = 0.7\text{ V} each). (3)

(b) Derive/state the DC output for an ideal full-wave bridge and compute VDCV_{DC} using your peak value. (2)

(c) Determine the minimum Peak Inverse Voltage (PIV) rating each diode must withstand, and justify it from the circuit topology. (3)

(d) The load draws 0.5 A0.5\text{ A}. Choose a reservoir capacitor for a peak-to-peak ripple of 1 V1\text{ V} using VrippleI/(frippleC)V_{ripple} \approx I/(f_{ripple}C). Compute CC. (2)


Question 3 — Zener regulator from scratch (12 marks)

Design a shunt Zener regulator: unregulated input Vin=15 VV_{in} = 15\text{ V} (varying ±2 V\pm 2\text{ V}), Zener VZ=6.2 VV_Z = 6.2\text{ V}, load current ILI_L ranging 1040 mA10\text{–}40\text{ mA}. Zener parameters: IZ,min=5 mAI_{Z,min} = 5\text{ mA}, PZ,max=0.5 WP_{Z,max} = 0.5\text{ W}.

(a) Derive the design equation for the series resistor RSR_S that keeps the Zener in regulation across all input/load conditions. State which worst-case combination sizes RSR_S. (4)

(b) Compute a suitable value of RSR_S (single value). (4)

(c) Check the maximum Zener power dissipation for your chosen RSR_S under the worst case, and confirm it is within PZ,maxP_{Z,max}. (4)


Question 4 — Clipper/clamper analysis (10 marks)

(a) A biased positive clipper: input vin=10sin(ωt)v_{in} = 10\sin(\omega t) V, a silicon diode (Vf=0.7V_f=0.7) in series with a +3 V+3\text{ V} battery clips the positive peaks. Sketch/describe the output waveform and give the exact clipping level. (4)

(b) Derive the steady-state output of a negative clamper (diode + capacitor) fed with vin=5sin(ωt)v_{in}=5\sin(\omega t) V, ideal diode, assuming the capacitor fully charges. Give the output DC level and peak values. (4)

(c) Explain out loud why a clamper needs the RC time constant T\gg T (period). (2)


Question 5 — Diode logic + Schottky/LED reasoning (10 marks)

(a) Draw the truth table for a 2-input diode OR gate (inputs A,BA,B at 0 V0\text{ V} or 5 V5\text{ V}, common resistor to ground, Vf=0.7V_f=0.7). State the output voltage for a HIGH. (4)

(b) Explain out loud why diode logic cannot be cascaded indefinitely (2 reasons). (2)

(c) A Schottky diode has Vf0.3 VV_f \approx 0.3\text{ V} and negligible reverse-recovery time. Give two circuit consequences of these properties vs a silicon PN diode. (2)

(d) An LED with Vf=2.0 VV_f = 2.0\text{ V} is run at 15 mA15\text{ mA} from a 5 V5\text{ V} rail. Compute the series resistor. (2)


Question 6 — Explain-out-loud: photodiode, varactor, datasheet (8 marks)

(a) Explain the operational difference between a photodiode in photovoltaic mode and photoconductive (reverse-biased) mode, and which suits fast, linear light sensing. (3)

(b) Explain how a varactor diode is used to tune an LC oscillator, and the role of reverse bias. (3)

(c) From a datasheet you read IR=5μAI_R = 5\,\mu\text{A}, Vf=1.1 V @ 1 AV_f = 1.1\text{ V @ }1\text{ A}, VRRM=100 VV_{RRM}=100\text{ V}. State what each parameter constrains in a design. (2)


Answer keyMark scheme & solutions

Question 1 (10)

(a) Half-wave: diode conducts only for 0ωtπ0 \le \omega t \le \pi. VDC=12π02πvod(ωt)=12π0πVmsin(ωt)d(ωt)V_{DC} = \frac{1}{2\pi}\int_0^{2\pi} v_o\, d(\omega t) = \frac{1}{2\pi}\int_0^{\pi} V_m\sin(\omega t)\, d(\omega t) (1 mark setup; 1 for limits — only half cycle passes) =Vm2π[cosωt]0π=Vm2π(1(1))=Vm2π(2)=Vmπ= \frac{V_m}{2\pi}[-\cos\omega t]_0^{\pi} = \frac{V_m}{2\pi}(1-(-1)) = \frac{V_m}{2\pi}(2) = \frac{V_m}{\pi} VDC=Vmπ0.318Vm\boxed{V_{DC} = \frac{V_m}{\pi} \approx 0.318\,V_m} (2 marks evaluation/result)

(b) Vrms=12π0πVm2sin2(ωt)d(ωt)V_{rms} = \sqrt{\frac{1}{2\pi}\int_0^{\pi} V_m^2\sin^2(\omega t)\,d(\omega t)} Using 0πsin2=π/2\int_0^\pi \sin^2 = \pi/2: =Vm22ππ2=Vm24=Vm2= \sqrt{\frac{V_m^2}{2\pi}\cdot\frac{\pi}{2}} = \sqrt{\frac{V_m^2}{4}} = \frac{V_m}{2}. Vrms=Vm2\boxed{V_{rms} = \frac{V_m}{2}} (1 setup, 1 integral value, 1 result)

(c) Half-wave passes one pulse per input cycle → ripple fundamental = supply frequency (50 Hz). Full-wave inverts the negative half so two pulses per input cycle → ripple = 2× supply (100 Hz). Higher ripple frequency ⇒ smaller reservoir capacitor for same ripple. (3 marks for the two-pulses-per-cycle reasoning.)

Question 2 (10)

(a) Vm=122=16.97 VV_m = 12\sqrt{2} = 16.97\text{ V}. (1) Bridge: two diodes conduct in series each half cycle, so Vpeak,out=16.972(0.7)=15.57 VV_{peak,out} = 16.97 - 2(0.7) = 15.57\text{ V}. (2)

(b) Ideal full-wave: VDC=2VmπV_{DC} = \frac{2V_m}{\pi}. Using loaded peak 15.5715.57: VDC=2(15.57)π=9.91 VV_{DC} = \frac{2(15.57)}{\pi} = 9.91\text{ V}. (Using ideal 16.9716.97: 10.8010.80 V — accept either with stated assumption.) (2)

(c) PIV: in a bridge, the two non-conducting diodes see the peak secondary voltage across them (the conducting pair short the bridge to the rail). PIV=Vm=16.97 V\text{PIV} = V_m = 16.97\text{ V} (≈17 V). Choose ≥ 2× margin ⇒ e.g. 50 V diodes. (Award full even if student states PIV = VmV_m for bridge vs 2Vm2V_m for centre-tapped.) (3)

(d) fripple=100 Hzf_{ripple} = 100\text{ Hz}. C=IfrippleVripple=0.5100×1=5×103=5000μFC = \frac{I}{f_{ripple}V_{ripple}} = \frac{0.5}{100 \times 1} = 5\times10^{-3} = 5000\,\mu\text{F}. (2)

Question 3 (12)

(a) KCL: IRS=IZ+ILI_{RS} = I_Z + I_L. Zener stays regulated if IZ,minIZIZ,maxI_{Z,min} \le I_Z \le I_{Z,max}. RSR_S must be small enough that even at minimum input & maximum load, IZIZ,minI_Z \ge I_{Z,min}: RSVin,minVZIZ,min+IL,maxR_S \le \frac{V_{in,min} - V_Z}{I_{Z,min} + I_{L,max}} Worst case for keeping Zener alive = lowest VinV_{in} (least available current) with highest ILI_L (load hogs current). (4)

(b) Vin,min=13 VV_{in,min} = 13\text{ V}, IL,max=40 mAI_{L,max}=40\text{ mA}: RS136.2(5+40) mA=6.80.045=151ΩR_S \le \frac{13 - 6.2}{(5+40)\text{ mA}} = \frac{6.8}{0.045} = 151\,\Omega Choose RS=150ΩR_S = 150\,\Omega (standard, satisfies ≤151). (4)

(c) Worst-case Zener power = maximum input, minimum load (max current diverted into Zener). Vin,max=17 VV_{in,max}=17\text{ V}, IL,min=10 mAI_{L,min}=10\text{ mA}: IRS=176.2150=10.8150=72 mAI_{RS} = \frac{17-6.2}{150} = \frac{10.8}{150} = 72\text{ mA} IZ,max=7210=62 mAI_{Z,max} = 72 - 10 = 62\text{ mA} PZ=VZIZ,max=6.2×0.062=0.384 W<0.5 WP_Z = V_Z I_{Z,max} = 6.2 \times 0.062 = 0.384\text{ W} < 0.5\text{ W} \checkmark (2 for identifying worst case, 2 for computation & verdict.)

Question 4 (10)

(a) Positive clipper with series diode + 3 V battery: output follows input until vinv_{in} exceeds the clip level. Clipping level = Vbattery+Vf=3+0.7=3.7 VV_{battery} + V_f = 3 + 0.7 = 3.7\text{ V}. Output = vinv_{in} for vin<3.7v_{in} < 3.7 V, clamped flat at 3.73.7 V for the portion above. Negative half (10-10 V peak) passes unaffected. (2 for level, 2 for waveform description.)

(b) Negative clamper (diode conducts on positive half, charging C to +Vm=5+V_m = 5 V; diode then off, capacitor voltage in series shifts waveform down). Steady state: vout=vinVm=5sin(ωt)5v_{out} = v_{in} - V_m = 5\sin(\omega t) - 5 Peaks: max =0= 0 V, min =10= -10 V, DC level =5= -5 V. (2 derivation, 2 values.)

(c) RC ≫ T so the capacitor barely discharges between cycles, holding its charge ⇒ the DC shift stays constant and waveform shape is preserved (no droop/distortion). (2)

Question 5 (10)

(a) Diode OR (anodes to inputs, cathodes common to output, R to ground). Output HIGH when any input HIGH; VOH=50.7=4.3 VV_{OH} = 5 - 0.7 = 4.3\text{ V}.

A B Out
0 0 0 V
0 5 4.3 V
5 0 4.3 V
5 5 4.3 V

(2 truth table, 2 for VOH=4.3V_{OH}=4.3 V/HIGH level.)

(b) (i) Each stage drops VfV_f (~0.7 V), so logic levels degrade after every stage. (ii) No signal gain / no active restoration ⇒ noise margin shrinks and levels drift; loading of later stages pulls levels further. (2)

(c) (1) Lower VfV_f (0.3 V) ⇒ less forward loss / better efficiency in low-voltage rectifiers. (2) Negligible reverse recovery ⇒ works at high switching frequencies (fast switch-mode rectifiers, RF). (2)

(d) R=52.00.015=3.00.015=200ΩR = \frac{5 - 2.0}{0.015} = \frac{3.0}{0.015} = 200\,\Omega. (2)

Question 6 (8)

(a) Photovoltaic mode: zero bias, the diode generates voltage/current from light (solar-cell-like), lower noise but slower/less linear. Photoconductive mode: reverse-biased, wider depletion region ⇒ lower capacitance, faster response, current linear with illumination — suits fast, linear sensing. (3)

(b) A varactor is a reverse-biased diode whose depletion-layer width (and hence junction capacitance CjC_j) varies with reverse voltage. Placed in the LC tank, changing the DC reverse bias changes CC and thus the resonant frequency f=1/(2πLC)f = 1/(2\pi\sqrt{LC}) — enabling voltage-controlled tuning (VCO/PLL). Reverse bias is essential to avoid conduction and to set CjC_j. (3)

(c) IRI_R (reverse leakage) constrains reverse/off-state losses & sensor noise floor; Vf@IV_f @ I constrains forward power dissipation/heat; VRRMV_{RRM} constrains the maximum reverse voltage (PIV) the diode can block. (2)

[
  {"claim":"Half-wave ideal Vdc = Vm/pi = 0.3183 Vm","code":"wt=symbols('wt'); Vm=symbols('Vm',positive=True); Vdc=integrate(Vm*sin(wt),(wt,0,pi))/(2*pi); result=simplify(Vdc-Vm/pi)==0"},
  {"claim":"HW rms output = Vm/2","code":"wt=symbols('wt'); Vm=symbols('Vm',positive=True); Vrms=sqrt(integrate((Vm*sin(wt))**2,(wt,0,pi))/(2*pi)); result=simplify(Vrms-Vm/2)==0"},
  {"claim":"Zener RS<=151 ohm at worst case (13-6.2)/0.045","code":"R=(13-6.2)/0.045; result=abs(R-151.11)<1"},
  {"claim":"Zener max power 0.384 W under Vin=17,IL=10mA,RS=150","code":"Irs=(17-6.2)/150; Iz=Irs-0.010; Pz=6.2*Iz; result=abs(Pz-0.384)<0.01 and Pz<0.5"},
  {"claim":"LED resistor (5-2)/0.015 = 200 ohm","code":"R=(5-2.0)/0.015; result=abs(R-200)<1e-6"},
  {"claim":"Bridge Vdc loaded = 2*(12*sqrt(2)-1.4)/pi approx 9.91","code":"Vdc=2*(12*sqrt(2)-1.4)/pi; result=abs(float(Vdc)-9.91)<0.05"}
]