6.5.7 · D4 · HinglishAdvanced & Emerging Architectures

ExercisesGoogle TPU architecture and systolic arrays

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6.5.7 · D4 · Hardware › Advanced & Emerging Architectures › Google TPU architecture and systolic arrays


Level 1 — Recognition

Recall Solution

KYA: "Systolic" systole se aaya hai, yani heartbeat — woh contraction jo blood pump karti hai. Metaphor kyun: jaise heartbeat blood ko rhythmically chamber se chamber mein push karti hai, array data ko rhythmically, ek hop per clock, ek cell se neighbouring cell mein push karta hai. Koi bhi cell computation ke beech global memory tak nahi pahunchti; sab kuch hand-to-hand pass hota hai. Captured key property: local, rhythmic dataflow with maximal reuse.

Recall Solution
  • Weights ruk jaate hain (yahi "weight-stationary" ka matlab hai) — har cell poori computation ke liye ek weight hold karta hai.
  • Activations horizontally move karti hain (left → right), ke zariye pass hoti hain.
  • Partial sums vertically move karte hain (top → bottom), har cell apna product add karta hai: .

Level 2 — Application

Recall Solution

KYA: mein plug karo. Factor 2 kyun: har cell ek clock mein ek MAC complete karta hai = 1 multiply + 1 add = 2 ops. TOPS mein convert karo ( ops/s): .

Recall Solution

KYA: cycles. Wasted fraction: fill/drain part cycles ka hai, toh Kyun matter karta hai: ek paanchwa hissa sirf pipeline fill karne mein gaya — yeh ek warning hai ki is array par chhote batches inefficient hain (ise hum L3 mein directly tackle karte hain).

Recall Solution

KYA — MACs count karo: ek product MACs karta hai, yahan . Naïve reads: har MAC ka 1 element aur ka 1 element padhta hai → reads. Systolic reads: inputs mein se har ek exactly ek baar padha jaata hai. KYun: reuse factor array dimension ke barabar hai — har operand cells mein se guzra jaane se pehle.


Level 3 — Analysis

Recall Solution

KYA: solve karo. Multiply out karo: , toh , milta hai Round up karo: rows. KYun: fixed 511-cycle fill tabhi "dilute" hoti hai jab useful stream use vastly outnumber kare. Zyada utilisation targets exponentially bade batches demand karte hain — isliye TPUs throughput machines hain, latency machines nahi.

Recall Solution

KYA — cycles, phir seconds (time = cycles ÷ ):

  • A: cycles . Time .
  • B: cycles . Time . Winner: A, aur yeh wall-clock time mein ~4.45× faster hai. KYun: equal peak throughput clock ko hide karta hai. B apna peak sirf perfect steady state mein reach karta hai; uska slow clock har cycle ko stretch karta hai, aur uska bada array zyada fill pay karta hai. Peak FLOP/s ek ceiling hai, delivered time nahi.
Figure — Google TPU architecture and systolic arrays

Level 4 — Synthesis

Recall Solution

KYA — N pick karo: . (Square yahan forced hai kyunki poora budget ek square array hai.) Peak: — bilkul TPUv1 ballpark. Utilisation for : fill ; Tension: ek fixed cell budget ke saath, bada peak throughput badhata hai (∝ ) lekin fill cost () bhi badhata hai, jo modest batches par utilisation hurt karta hai. par yeh 256-array sirf do-tihai efficient chalti hai — tum ya toh batch bada karte ya, agar latency-bound ho, chhoti array prefer karte. Koi free lunch nahi; tum peak ceiling aur fill overhead ke beech trade kar rahe ho. Iske general form ke liye Dataflow architectures dekho.

Recall Solution

KYA: array AI MACs/byte. Balance point se compare karo: kyunki , tum compute-bound ho (ek achhi jagah — tum DRAM se nahi, silicon se limited ho). Margin: balance point se aage. KYun: systolic layout ka poora reason AI ko itna high push karna hai ki memory wall clear ho sake; yahan tum use 2.56× se clear karte ho, toh zyada memory bandwidth add karna tumhe speed up nahi karega — sirf zyada/faster cells karengi.


Level 5 — Mastery

Recall Solution

KYA — build karo: ek batch mein useful MACs (har rows mein se ek sab cells ko ek baar drive karta hai). Total cycles , aur time . Toh KYun yeh shape hai: yeh exactly peak × utilisation hai. Jab , aur delivered (ceiling). par, tiny — single row fill amortise karne mein barely kamyab hota hai. Numbers: peak TOPS (4.1 se); ; Padho ise: tumne 91.75 TOPS ka silicon kharida lekin 61.2 deliver kiya — missing third pipeline fill mein leak ho gaya. Woh gap hi L3/L4 lesson hai quantitatively.

Figure — Google TPU architecture and systolic arrays
Recall Solution

(a) Inference ke liye 8-bit kyun kaafi hai: ek 8-bit multiplier 32-bit float multiplier se kaafi chhota aur kam-energy wala hai, toh tum usi silicon mein zyada MAC cells fit karte ho → zyada → zyada peak. Inference sirf ek forward pass chahta hai, aur ek achhi tarah se quantised network 8-bit weights/activations ko negligible accuracy loss ke saath tolerate karta hai (dekho Quantization and 8-bit inference). Zyada cells + adequate precision = TPUv1 ka bet. (b) Training ke liye 8-bit kyun fail hota hai: training mein gradient descent use hota hai; gradients tiny ho sakte hain aur kai steps par accumulate hote hain. Unhe 8-bit integers mein round karna un chhoti values ko throw away karta hai jo learning signal carry karti hain — model converge karna band kar deta hai. Training ko floating point chahiye wide dynamic range ke saath (bfloat16 float32 ke 8 exponent bits rakhta hai), isliye TPU v2+ switch kiya. Yahi precision-vs-range tension hai jo quantization note develop karta hai. Synthesis: precision ek dial hai, constant nahi — tum minimum precision spend karo jo task tolerate kare aur savings se throughput kharido. Inference kam tolerate karta hai; training gradients ki rounding kaafi kam tolerate karta hai.