6.3.11 · D1 · Hardware › Interconnects, Buses & SoC › Infinity Fabric - mesh interconnects
Ek modern CPU ke andar dozens of chhote "workers" hote hain (cores, caches, memory controllers) jo constantly ek doosre ko messages bhejte rehte hain, aur unke beech ki wiring ek chhoti si road network hai. Infinity Fabric aur mesh interconnects wahi road network hain — poora topic bus road ke shapes (bus, ring, grid) chunne ke baare mein hai taaki messages fast pohonche bina saari traffic ek hi road pe jam ho jaaye.
Is page pe assume kiya gaya hai ki aap kuch nahi jaante. Har letter, symbol, aur buzzword jo parent note mein aata hai, woh yahan order mein build kiya gaya hai, har ek ke saath ek picture. Upar se neeche padhte jaiye.
Road draw karne se pehle, humein jaanna hai ki un roads pe kaun chal raha hai.
Ek node chip ka koi bhi "box" hota hai jo messages send ya receive kar sakta hai: ek CPU core, ek cache ka piece, ek memory controller, ya ek I/O controller. Is page ki har picture mein ek node ko coloured square ke roop mein draw kiya gaya hai.
Ek core ek poora CPU brain hota hai — yeh aapke program instructions run karta hai. "8 cores" wale chip mein 8 aisi cheezein hoti hain, aur woh sab ek saath data chahte hain. Woh "ek saath" hi poori wajah hai ki humein ek clever network chahiye.
Cache ek chhoti, bahut fast memory hoti hai jo cores ke paas rehti hai aur recently-used data ko close rakhti hai. Ek badi shared cache ko slices ke naam se jaane waale pieces mein kaata jaata hai; har slice ek node ke paas rehti hai. Caches isliye matter karte hain kyunki do cores ek hi data ki copies hold kar sakte hain — aur copies aapas mein disagree kar sakti hain (hum section 8 mein isko fix karte hain).
Prerequisites ka building block: agar "core", "cache", aur "memory controller" words fuzzy lagte hain, toh 6.3.1-Bus-ArchitectureBasics mein wiring background ek achha companion hai — yeh page seedha usi pe build karta hai. (Hum har wiring word define karte hain jo hum use karte hain, jisme bus bhi shamil hai, section 2 mein neeche, toh aap yahan padhna jaari rakh sakte hain.)
Figure dekho: teen squares (ek core , ek cache slice , ek memory controller ) har ek ke paas ek chhota stub — woh stub plug-in point hai jahan baad mein ek road attach hogi. (Hum is plug-in point ko uska proper naam, port , section 3 mein denge.) In characters ko yaad rakho; neeche har topology sirf inhi squares ko rearrange karti hai.
Ab hum squares ko connect karte hain. Teen shapes hain jinhe parent note compare karta rehta hai.
Bus ek shared wire hoti hai jis pe har node hang karta hai. Ek time pe sirf ek hi node "baat" kar sakta hai — baaki sab wait karte hain. Socho ek single narrow corridor jahan logon ko baari baari jaana padta hai.
Ring nodes ko circle mein connect karti hai: har node sirf apne do neighbours se wire hota hai. Kisi door node tak message pahunchane ke liye beech ke har node se hop karna padta hai. Socho ek circular hallway — opposite wale room tak pahunchne ke liye aadha chakkar lagana padta hai.
Mesh nodes ka ek 2D grid hai. Har node apne neighbours se upar/neeche/left/right (North, South, East, West) wire hota hai. Socho city blocks: kisi bhi corner se kisi bhi doosre corner tak kai routes maujood hain.
Intuition Shape kyun matter karta hai
Bus (left) jam ho jaati hai kyunki sab ek wire share karte hain. Ring (middle) fair hai lekin dur ki trips ke liye slow hai. Mesh (right) shortcuts deta hai. Parent note ki poori "why fabric replaced rings and buses" story bas yeh hai: jaise hum cores add karte hain, bus jam ho jaati hai aur ring slow ho jaati hai, toh hum mesh ki taraf switch karte hain.
Topology simply "network ki shape" hai — pattern ki kaun sa node kis se connect hai. Bus, ring, aur mesh teen topologies hain. Data-center scale pe isi idea ke liye 7.2.4-Network-Topologies dekho.
"Fast" aur "slow" ke baare mein baat karne ke liye humein count karna hoga.
Ek hop ek node se next-door node tak message ka ek step hai. Kai nodes ke across ek trip ko number of hops mein measure kiya jaata hai. Ek hallway mein, ek hop = ek doorway se guzarna.
Definition Router (= switch)
Har grid intersection pe ek router hota hai: ek chhota traffic cop jo padhta hai ki ek message kahan jaana chahta hai aur usse sahi exit se bahar dhakelta hai. Intel ke mesh mein har router ke 5 ports hote hain.
⚠️ Aap switch word bhi dekhenge. Is topic mein "router" aur "switch" exact same component ko mean karte hain — ek tile pe chhota traffic cop. Hum puri jagah "router" use karte hain; jab bhi parent note "switch" use kare, bas synonym samjho.
Ek port ek router pe ek doorway hai. Intel ke mesh router ke 5 hain: North, South, East, West, aur ek local port jo neeche jaata hai us node tak jis pe woh baitha hai (apna core + cache slice). (Yeh woh "plug-in point" hai jo aapne figure s01 mein stub ke roop mein dekha tha.)
Figure ek single 5-port router dikhata hai. Chaar grey arrows neighbour routers ke compass directions hain; neeche jaata magenta arrow is router ke apne core ka local port hai. Parent note ka har mesh bas inhi tiles ko edge-to-edge wire karne se banta hai.
Ek tile = ek core + uski cache slice + uska router, ek repeatable unit ke roop mein package kiya gaya. Chip banao tiles ko grid mein stamp karke. Physically yahi "mesh interconnect" ka matlab hai.
Parent note ( 0 , 0 ) aur ( 3 , 2 ) jaise positions likhta hai aur hops compute karta hai. Yahan woh sab kya matlab rakhte hain.
Definition Grid coordinates
( x , y )
Har tile ko ek address do: x = kaun sa column (East ginke), y = kaun si row (North ginke). Bottom-left tile ( 0 , 0 ) hai. Yeh exactly chessboard square ko naam dene jaise hai. Humein coordinates chahiye taaki hum arithmetic se distances compute kar sakein baar baar dekhne ki jagah.
Yeh formula kyun, aur straight-line distance kyun nahi? Grid pe aap buildings ke aarpaar diagonally nahi cut kar sakte — aapko streets ke along chalha padta hai, East/West phir North/South. Toh honest hop count horizontal aur vertical legs ko jodta hai. Isliye iska naam Manhattan ke block layout ke naam pe rakha gaya hai.
Worked example Parent ka routing example padhna
( 0 , 0 ) se ( 3 , 2 ) tak: ∣3 − 0∣ + ∣2 − 0∣ = 3 + 2 = 5 hops. Yeh parent note ke 5 hops ke answer se match karta hai.
Common mistake Bars bhoolna mat
x 2 − x 1 ko ∣ ⋅ ∣ ke bina likhne par − 3 milta hai agar aap doosri taraf jaate ho. Distance kabhi negative nahi hoti — hamesha absolute value lo.
N — nodes ki sankhya
N simply kitne nodes hain (usually cores) chip pe. Parent N = 16 , N = 64 , etc. use karta hai. Latency aur bandwidth ke baare mein sab kuch N ke function ke roop mein likha jaata hai taaki formulas kisi bhi chip size ke liye kaam karein.
N — square mesh ki side, jise hum k kehte hain
Agar N nodes ek square grid banate hain, toh har side ke N nodes hote hain (kyunki side × side = area = N ). Hum is side-length ko apna chhota naam dete hain: k = N . Toh k simply hai "ek edge ke saath kitni tiles". N = 16 ke liye, k = 16 = 4 , ek 4 × 4 mesh deta hai. Jab bhi ab aap k dekhein, padhein "grid side = N ".
Common mistake Kya hoga agar
N perfect square nahi hai?
Neat formula k = N tabhi whole number deta hai jab perfect squares hon (16 , 25 , 36 , 64 … ). Real chips kabhi itne tidy nahi hote — ek "18-core" mesh square nahi ho sakta. Practice mein do cheezein hoti hain:
Rectangular meshes. Do side-lengths use karo, k x columns by k y rows, with k x ⋅ k y = N (e.g. 6 × 3 = 18 ). Averages cleanly generalise hote hain: column leg average ≈ k x /3 aur row leg ≈ k y /3 , toh avg hops ≈ ( k x + k y ) /3 . Square case bas k x = k y = N hai.
"Square" estimate round karna. Jab koi non-square N ke liye N quote karta hai toh unka matlab approximation hai; nearest rectangle ⌊ N ⌋ × ⌈ N / ⌊ N ⌋⌉ lo (floor ⌊ ⋅ ⌋ = round down, ceiling ⌈ ⋅ ⌉ = round up). Answer thoda hi shift hota hai.
Bottom line: k = N ko clean square special case treat karo; messy core counts ke liye k x , k y swap karo.
Parent note E [ ∣ x 2 − x 1 ∣ ] likhta hai. Ghabrao mat — yeh ek average hai.
E [ ⋅ ] — expected value
E [ something ] ka matlab hai "saare random cases mein something ki average value". Ise "typical" padhein.
Definition Uniform-traffic assumption
Ek clean number paane ke liye hum uniform random traffic assume karte hain: har source tile equally likely hai, aur har destination tile equally likely hai, independently. Yeh standard "no favourites" baseline hai. Real chips mein hot spots ho sakte hain (e.g. sab ek memory controller pe hammer kar rahe hain) — hum us edge case ko is section ke end mein handle karte hain.
E [ ∣ x 2 − x 1 ∣ ] = 3 k k 2 − 1 (column part) derive karna, step by step. Hum sirf x coordinate dekhte hain. Dono x 1 aur x 2 columns 0 , 1 , … , k − 1 se uniformly pick kiye jaate hain, toh har ek ke liye k choices hain — kul k 2 ordered pairs, har ek equally likely. Average hai sabhi gaps ka total divided by k 2 :
E [ ∣ x 2 − x 1 ∣ ] = k 2 1 S a = 0 ∑ k − 1 b = 0 ∑ k − 1 ∣ a − b ∣ .
Ab hum actually sum S compute karte hain , sirf quote nahi karte. Pairs ko unke gap g = ∣ a − b ∣ ke hisaab se group karo:
gap g = 0 : pairs jaise ( 0 , 0 ) , ( 1 , 1 ) , … — inke k hain, contributing 0 .
gap g = 1 : pairs ( 0 , 1 ) , ( 1 , 0 ) , ( 1 , 2 ) , ( 2 , 1 ) , … — k − 1 adjacent positions mein se har ek ke liye 2 orderings hain, toh 2 ( k − 1 ) pairs, har ek contributing 1 .
gap g generally: k − g starting positions hain aur 2 orderings, toh 2 ( k − g ) pairs, har ek contributing g .
Inhe jodte hain:
S = g = 1 ∑ k − 1 g ⋅ 2 ( k − g ) = 2 g = 1 ∑ k − 1 ( k g − g 2 ) .
Dono schoolbook sums use karo ∑ g = 1 k − 1 g = 2 ( k − 1 ) k aur ∑ g = 1 k − 1 g 2 = 6 ( k − 1 ) k ( 2 k − 1 ) :
S = 2 [ k ⋅ 2 ( k − 1 ) k − 6 ( k − 1 ) k ( 2 k − 1 ) ] = 3 ( k − 1 ) k ( k + 1 ) = 3 k ( k 2 − 1 ) .
k 2 se divide karo:
E [ ∣ x 2 − x 1 ∣ ] = k 2 S = k 2 k ( k 2 − 1 ) /3 = 3 k k 2 − 1 ≈ 3 k .
Bade k ke liye − 1 negligible hai, tidy 3 k deta hai jo parent quote karta hai. Useful 3 1 seedha ∑ g 2 step se nikla.
Row part identical hai (bas x ki jagah y swap karo), aur ek aur 3 k milta hai. Kyunki Manhattan distance dono legs jodta hai:
avg hops = 3 k + 3 k = 3 2 k = 3 2 N .
Recall Ring ka
4 1 N kahan se aata hai? (Full derivation)
N nodes ki ring pe, ek fixed source se target ek direction mein n nodes door baitha hai, lekin aap hamesha shorter arc lete ho, toh true distance min ( n , N − n ) hai. Sabhi N equally-likely targets pe average karo:
avg = N 1 ∑ n = 0 N − 1 min ( n , N − n ) .
Sum ko halfway point pe split karo (N even lo). n = 0 … 2 N ke liye shorter arc hi n hai; n = 2 N … N − 1 ke liye yeh neeche mirror karta hai. 0 se 2 N tak har value essentially do baar appear hoti hai, toh
∑ n = 0 N − 1 min ( n , N − n ) = 2 ∑ n = 1 N /2 − 1 n + 2 N = 2 ⋅ 2 ( N /2 − 1 ) ( N /2 ) + 2 N = 4 N 2 .
(Middle sum ∑ n = 1 m n = 2 m ( m + 1 ) with m = 2 N − 1 kaam karta hai; leftover 2 N single un-mirrored halfway node hai.) N se divide karo:
avg hops (ring) = N 1 ⋅ 4 N 2 = 4 N .
Toh 4 1 genuinely sum ∑ min ( n , N − n ) = N 2 /4 divided by N hai — distances evenly 0 se N /2 tak spread hoti hain, aur us spread ka midpoint N /4 hai.
Common mistake Uniform ek
model hai, law nahi
Agar traffic non-uniform hai — maano har core repeatedly ek "home" memory controller hit karta hai — toh k /3 aur N /4 averages reality describe nahi karte; us hot node ke links bottleneck ban jaate hain. Real designs precisely isi se ladne ke liye extra links add karte hain ya home nodes spread karte hain. Hamesha yaad rakho averages no-favourites assume karte hain.
Parent ke worked examples bytes ko frequency se multiply karte hain. Yahan har piece hai.
Definition Clock frequency (GHz)
Ek clock ek metronome hai jo billions of times per second tick karta hai. 1 GHz = 1 billion ticks (cycles) per second. Har tick pe, hardware data ka ek batch move karta hai.
Definition FCLK — Fabric Clock
FCLK woh clock hai jo specifically Infinity Fabric drive karta hai. Zyada FCLK ka matlab hai fabric ke across per second zyada data batches. (MCLK memory clock hai; parent unke 1:1 ya 2:1 ratio ke baare mein baat karta hai.)
Definition Bus width (bytes per cycle)
Width hai kitne bytes road har tick pe carry karta hai. "32 B wide" fabric har cycle mein 32 bytes move karta hai. Chaudi road = per tick zyada.
Worked example Parent ka Example 1 reproduce karna
Ek direction: 32 × 1.8 = 57.6 GB/s.
Dono directions ek saath (data dono ways flow kar sakta hai): 2 × 57.6 = 115.2 GB/s. ✓
2 se kyun multiply karte hain? Link ke paas send aur receive ke liye alag alag wires hain, toh dono directions simultaneously run karte hain — total double milta hai.
Is arithmetic ke memory-side ke liye, 5.1.7-Memory-BandwidthCalculation dekho.
Definition Bisection bandwidth
Network ko cleanly do halves mein kaato aur woh roads gino jo cut cross karte hain. Bisection bandwidth = ek baar mein dono halves ke beech kitna data flow kar sakta hai. Yeh worst-case chokepoint measure karta hai.
Ring: koi bhi straight cut exactly 2 links kaatta hai (circle do jagah cross hoti hai).
k × k mesh (with k = N ): do columns ke beech slice karo aur aap har row mein ek link kaatte ho — yeh k = N links hain.
Toh general rule hai: ring bisection = 2 links, mesh bisection = N links. N = 16 ke liye woh 16 = 4 mesh links versus 2 ring links hai → mesh ke paas 2 × bisection bandwidth hai, aur yeh gap N ke saath barhta hai.
Definition Cache coherence
Jab do cores ek hi data ki copy rakhte hain, coherence woh rule-system hai jo un copies ko agreement mein rakhta hai — taaki koi stale data na padhe jab kisi doosre ne write kar diya ho. Iske bina, ek core ek value "correct" kar sakta hai jo doosra core kabhi change hote nahi dekhta.
Definition Directory vs broadcast
Broadcast snoop : update har core ko chillao. Traffic N ke saath barhta hai — shor wala.
Directory-based : ek bookkeeper ("home" cache slice) exactly kinse cores ke paas copy hai record karta hai, aur sirf unhi thode se cores ko message bhejta hai. Traffic sharers ki sankhya k s ke saath barhta hai (usually 1–3) — shant. (Hum yahan k s likhte hain taaki section 5 ke grid side k se clash na ho.)
Infinity Fabric directory idea use karta hai taaki coherence 64 cores ke saath bhi sasta rahe. Deep dive: 6.3.5-Cache-Coherency-Protocols .
Ek piece of data ka home node woh fixed cache slice hai jo use track karne ka responsible hai. Us data ka har request pehle uske home se guzarta hai — jaise kisi address ke liye har parcel ek local post office se guzarta hai.
Ek chiplet ek chhota alag silicon die hai jisme cores ka ek cluster hota hai. AMD bade CPUs banata hai kaafi chiplets ko Infinity Fabric se jodhke instead of ek giant die banane ke (sasta, better yield).
Definition NUMA (Non-Uniform Memory Access)
Kyunki chiplets alag alag distances pe baithte hain, nearby memory reach karna fast hai aur far memory slower hai — access time non-uniform hai. Yahi 6.2.8-NUMA-Architecture idea hai, aur isliye parent note carefully "worst-case chiplet 0 → chiplet 7" hop cost count karta hai.
Definition xGMI / IFIS link
Woh named wire jo dies ya packages ke beech Infinity Fabric carry karta hai. xGMI stands for inter-Chip Global Memory Interconnect ("x" = inter/cross, "GMI" = Global Memory Interconnect; on-package version plain GMI hai). IFIS stands for Infinity Fabric Inter-Socket — wahi fabric do physical CPU packages ke beech socket-to-socket link mein extend hoti hai. Dono ko do alag city grids ke beech highway bridge samjho: har die ke andar tiles local mesh pe baat karte hain, aur xGMI/IFIS traffic gap ke across carry karta hai. Isi tarah PCIe jaise external devices chip ke fabric mein reach karte hain.
Intuition Irregular meshes kyun hote hain
Silicon die ek rectangle hai, aur memory controllers aur I/O uske edges ke saath fixed spots pe land karte hain — tidy grid pe nahi. Toh real "meshes" often irregular hote hain: mostly-rectangular grid jisme kuch tiles missing hain, edge-mounted controller tak pahunchne ke liye extra links, ya die shape match karne ke liye non-uniform row/column counts.
Definition Irregular / non-rectangular mesh
Ek mesh jiske tiles perfect k × k (ya even k x × k y ) rectangle nahi banate: kuch grid positions empty hain, ya extra "express" links rows skip karte hain I/O agent tak jaldi pahunchne ke liye. Section 3 se router-and-port machinery unchanged hai — sirf pattern badalta hai ki kaun sa router kisse wire hota hai.
Common mistake Clean formulas best-case guides hain
3 2 N hops aur N bisection links ek perfect square mesh assume karte hain uniform traffic ke saath. Ek irregular die-shaped mesh pe, real average hops aur bisection actual layout pe measure karne padenge — formulas ek ballpark dete hain, guarantee nahi. Designers inhe topology choices compare karne ke liye use karte hain, phir exact chip simulate karte hain.
coordinates and Manhattan distance
averages E of hops k over 3
bisection bandwidth sqrt N
cache coherence directory home
rectangular and irregular meshes
Infinity Fabric and mesh interconnects
Ise padhein: raw players tiles bante hain, tiles ek topology mein arrange hote hain, hum us topology ko hops aur coordinates se measure karte hain, ise N aur k = N (ya k x , k y ) se size karte hain, E se average karte hain, bandwidth se uski speed price karte hain, coherence se iske copies honest rakhte hain, aur finally accept karte hain ki real dies irregular grids use karte hain — yeh sab milke parent topic mein combine hote hain.
Right side cover karo; kya aap parent note par jaane se pehle har ek answer de sakte ho?
Node ek sentence mein kya hai?Chip pe koi bhi box (core, cache slice, memory/I-O controller) jo messages send ya receive karta hai.
Bus jam kyun hoti hai lekin mesh nahi? Bus ek shared wire hai toh ek time pe sirf ek node baat kar sakta hai; mesh kai parallel roads aur shortcuts deta hai.
Hop kya hai?Node se uske immediate neighbour tak message ka ek step.
Kya "router" aur "switch" yahan different cheezein mean karte hain? Nahi — is topic mein woh same component hain, tile pe 5-port traffic cop.
Intel mesh router ke kitne ports hote hain, aur woh kya hain? 5 — North, South, East, West, aur apne core/cache ka ek local port.
( x 1 , y 1 ) se ( x 2 , y 2 ) tak Manhattan distance likho.d = ∣ x 2 − x 1 ∣ + ∣ y 2 − y 1 ∣ .
N nodes ke square mesh mein side length k kya hai?Agar N perfect square nahi hai toh? Rectangular mesh k x × k y use karo with k x k y = N ; avg hops ≈ ( k x + k y ) /3 .
E [ ⋅ ] ka matlab kya hai?Sabhi random cases mein average (typical) value.
Average column gap ( k 2 − 1 ) / ( 3 k ) ≈ k /3 kyun hai? Pairs ko gap g se group karne par S = ∑ g 2 ( k − g ) g = k ( k 2 − 1 ) /3 milta hai; k 2 se divide karne par ( k 2 − 1 ) / ( 3 k ) milta hai.
Ring ka N /4 kahan se aata hai? ∑ n min ( n , N − n ) = N 2 /4 ; N se divide karne par N /4 milta hai.
Kaun sa assumption k /3 aur N /4 valid banata hai, aur kya use todta hai? Uniform random traffic (no favourites); hot-spot / non-uniform traffic ise tod deta hai.
Bandwidth formula do. Bandwidth = bus width (bytes) × clock frequency (cycles per second); bidirectional ke liye double karo.
32 B fabric at 1.8 GHz ki one-direction bandwidth calculate karo. 32 × 1.8 = 57.6 GB/s.
N × N mesh vs ring ki bisection width kya hai?Mesh
= N links, ring
= 2 links.
Directory vs broadcast coherence — kaun sa better scale karta hai aur kyun? Directory, kyunki yeh sirf thode sharers ko message karta hai (O ( k s ) ) instead of har core ko (O ( N ) ).
xGMI ka kya matlab hai, aur IFIS? xGMI = inter-Chip Global Memory Interconnect (die-to-die); IFIS = Infinity Fabric Inter-Socket (package-to-package).
Real meshes irregular kyun ho jaate hain? Die ek rectangle hai jisme I/O aur memory controllers edges pe fixed hote hain, toh grid mein missing tiles aur extra links aa jaate hain die shape match karne ke liye.
Ready ho? parent topic pe wapas jaao — wahan ka har symbol ab tumhara hai.