Direct Memory Access (DMA) ek hardware mechanism hai jo peripheral devices ko memory mein data directly transfer karne deta hai bina CPU ke continuous intervention ke. DMA controller woh specialized hardware hai jo in transfers ko orchestrate karta hai.
CPU peripheral register se read karta hai (1 instruction)
CPU memory address mein write karta hai (1 instruction)
CPU pointers increment karta hai (1-2 instructions)
CPU check karta hai ki kaam ho gaya (1 instruction)
Har byte ke liye repeat
1 MB transfer mein 1 byte per iteration ke hisaab se ~5 million instructions chahiye. 1 GHz pe 5 cycles per iteration ke saath, ye 25 milliseconds of pure CPU time data shuffling mein waste hoti hai.
DMA ke saath:
CPU ek baar DMA controller program karta hai (~10 instructions)
DMA controller poora transfer hardware mein perform karta hai
CPU concurrently useful kaam karta hai
DMA interrupt ke through completion signal karta hai
Ye kyun matter karta hai: Modern SSDs 3+ GB/s pe transfer kar sakte hain. DMA ke bina, CPU 100% occupied rehta sirf data copy karne mein, applications ke liye zero cycles bacha ke.
Controller ko autonomously memory transfer perform karne ke liye pata hona chahiye:
Kahan se read karna hai → SAR starting source address store karta hai
Kahan write karna hai → DAR starting destination address store karta hai
Kitna transfer karna hai → BCR remaining byte count store karta hai
Kaise transfer karna hai → CSR mode bits store karta hai (direction, width, burst size)
Har register CPU ke dwara hardware-writable hona chahiye (setup ke liye) aur DMA logic ke dwara hardware-readable/writable (transfer ke dauran auto-increment ke liye).
\text{bit 0} & \text{Enable (EN): 1 = start transfer} \\
\text{bit 1} & \text{Interrupt Enable (IE): 1 = IRQ on completion} \\
\text{bits 2-3} & \text{Transfer Width: 00=byte, 01=halfword, 10=word} \\
\text{bits 4-5} & \text{Direction: 00=M2M, 01=M2P, 10=P2M} \\
\text{bit 6} & \text{Increment SAR (0=fixed, 1=increment)} \\
\text{bit 7} & \text{Increment DAR} \\
\text{bits 8-15} & \text{Burst Length (0-255 transfers per burst)} \\
\text{bit 31} & \text{Done (D): 1 = transfer complete (read-only)}
\end{cases}$$
**Ye specific bits kyun?**
- **EN bit**: Hardware AND gate transfer state machine ko enable karta hai
- **Transfer width**: Address increment control karta hai (SAR += 1/2/4 bytes) aur bus transaction size
- **Burst length**: Bus monopolization vs. setup overhead ka tradeoff karta hai (dekho Burst Transfers section)
## DMA Kaise Kaam Karta Hai: Step-by-Step
### Setup Phase (CPU-initiated)
```
1. CPU source address ko SAR mein likhta hai
Kyun? DMA ko pata hona chahiye data kahan hai
2. CPU destination address ko DAR mein likhta hai
Kyun? DMA ko pata hona chahiye data kahan jaayega
3. CPU transfer size ko BCR mein likhta hai
Kyun? DMA ko termination condition chahiye
4. CPU control bits ko CSR mein likhta hai (width, direction, burst)
Kyun? Transfer mode configure karta hai
5. CPU CSR mein EN bit set karta hai → Transfer shuru
Kyun? DMA FSM activate karne ke liye hardware signal
```
### Transfer Phase (Hardware-controlled)
DMA controller **finite state machine** ki tarah operate karta hai:
> [!formula] DMA Transfer State Machine
$$\text{State 0 (IDLE)}: \text{EN=0, wait for enable}$$
$$\downarrow \text{EN=1}$$
$$\text{State 1 (REQUEST)}: \text{Assert bus request signal, wait for grant}$$
$$\downarrow \text{Bus granted}$$
$$\text{State 2 (TRANSFER)}: \begin{cases}
\text{Place SAR on address bus} \\
\text{Assert READ signal} \\
\text{Capture data} \\
\text{Place DAR on address bus} \\
\text{Place data on bus} \\
\text{Assert WRITE signal} \\
\text{SAR += width, DAR += width, BCR -= width}
\end{cases}$$
$$\downarrow \text{If BCR} \neq 0$$
$$\text{Repeat State 2 (or go to State 1if cycle-stealing)}$$
$$\downarrow \text{If BCR} = 0$$
$$\text{State 3 (DONE)}: \text{Set Done bit, trigger IRQ if IE=1, return to IDLE}$$
**Ye design kyun?**
- **Bus request/grant**: DMA ek bus master hai, CPU ke saath arbitrate karna padta hai
- **Registers ka atomic read-modify-write**: Multi-step transfers mein race conditions se bachata hai
- **BCR countdown**: Hardware comparator BCR=0 check karta hai terminate karne ke liye
### Completion Phase
> [!example] DMA Completion Sequence
> Scenario: SD buffer se RAM mein 1 KB transfer karo
```
1. 1024 bytes transfer hone ke baad BCR 0 pe pahunchta hai
Kyun? Hardware har cycle mein BCR decrement karta hai
2. DMA controller CSR.Done = 1 set karta hai
Kyun? Status bit CPU polling ya interrupt handler ko visible hota hai
3. Agar CSR.IE = 1, DMA interrupt line assert karta hai
Kyun? CPU ko asynchronous notification
4. CPU interrupt handler CSR.Done read karta hai, completion confirm karta hai
Kyun? Data use karne se pehle verify karo ki transfer succeed hua
5. Handler CSR.EN clear karta hai (acknowledge)
Kyun? Agले transfer ke liye reset
```
## Transfer Modes
### 1. Burst Mode (Block Transfer)
> [!formula] Burst Mode Timing
> DMA bus acquire karta hai aur poora transfer complete hone tak hold karta hai:
$$T_{\text{burst}} = T_{\text{setup}} + N \times T_{\text{cycle}}$$
Jahaan:
- $T_{\text{setup}}$ = bus arbitration + first address setup (typically 2-5 cycles)
- $N$ = transfers ki sankhya (BCR / width)
- $T_{\text{cycle}}$ = time per transfer (typically 1-2 bus cycles for back-to-back)
**Burst mode kyun use karo?**
- **Minimum overhead**: Setup cost kaafi transfers pe amortize ho jaata hai
- **Maximum throughput**: Transfers ke beech koi arbitration nahi
**Burst mode hamesha kyun nahi?**
- **CPU starvation**: Agar DMA transfer 1000 cycles leta hai, CPU 1000 cycles wait karta hai
- **Doosre masters ke saath unfair**: Doosre devices bus access nahi kar sakte
> [!example] Burst Mode Calculation
> 4 KB transfer at 32-bit width, 100 MHz bus:
> - $N = 4096 / 4 = 1024$ transfers
> - $T_{\text{setup}} = 4$ cycles (typical)
> - $T_{\text{cycle}} = 1$ cycle (zero-wait SDRAM)
> - $T_{\text{burst}} = 4 + 1024 = 1028$ cycles = **10.28 μs**
> - CPU poore 10.28 μs ke liye blocked
### 2. Cycle Stealing Mode
> [!formula] Cycle Stealing Timing
> DMA **ek baar ke transfer** ke liye bus request karta hai, release karta hai, phir repeat:
$$T_{\text{cycle-steal}} = N \times (T_{\text{arb}} + T_{\text{transfer}})$$
Jahaan:
- $T_{\text{arb}}$ = arbitration overhead per transfer (2-3 cycles)
- $T_{\text{transfer}}$ = actual data movement (1-2 cycles)
**Ye step kyun?** Har transfer ke liye bus request aur release karna padta hai.
Total time: $1024 \times (3 + 1) = 4096$ cycles = **40.96 μs**
**Tradeoff analysis:**
- **Throughput**: Burst se 4× slow (arbitration overhead ki wajah se)
- **Latency**: CPU DMA cycles ke beech bus access kar sakta hai → better responsiveness
- **Fairness**: CPU ~50% bus cycles milte hain (agar DMA aur CPU alternate karein)
### 3. Transparent Mode
DMA bus monitor karta hai aur tabhi transfer karta hai jab CPU **bus use nahi kar raha** (jaise, internal ALU operations ke dauran).
**Ye kyun kaam karta hai:** Modern CPUs har cycle mein external bus access nahi karte:
- Cache hits external bus use nahi karte
- Internal register operations bus use nahi karti
- In cycles ke dauran, DMA ek transfer "sneak in" kar sakta hai
**Limitation:** Transfer rate CPU bus utilization pe depend karta hai. Agar CPU 90% bus-active hai, DMA sirf 10% milta hai → slow aur unpredictable.
## Bus Arbitration
> [!formula] DMA Priority Schemes
**Fixed Priority:**
$$\text{Priority order: CPU} > \text{DMA}_1 > \text{DMA}_2 > \ldots$$
Simple hardware: daisy-chain grant signal. Lekin lower-priority devices starve ho sakte hain.
**Rotating Priority (Round-Robin):**
$$\text{After device } i \text{ uses bus, priority becomes: } (i+1) \bmod N > (i+2) \bmod N > \ldots$$
Fair, lekin complex (priority tracking register chahiye).
**Ye kyun matter karta hai:** Ek disk DMA controller aur network DMA controller dono ko high throughput chahiye. Fixed priority matlab ek starve hoga; rotating priority ensure karta hai dono ko service mile.
## Addressing Modes
### Increment Mode
```
SAR = 0x1000, width = 4bytes
Transfer 1: Read from0x1000, SAR → 0x1004
Transfer 2: Read from 0x1004, SAR → 0x1008
...
```
**Kyun?** Contiguous memory regions (arrays, buffers).
### Fixed Mode
```
SAR = 0x1000 (peripheral FIFO register)
Transfer 1: Read from 0x1000, SAR stays 0x1000
Transfer 2: Read from 0x1000, SAR stays 0x1000
...
```
**Kyun?** Peripheral ka single data register hota hai jo hamesha next byte hold karta hai (UART RX FIFO, ADC result register).
## Scatter-Gather DMA
> [!definition] Scatter-Gather
> Advanced DMA controllers ==descriptor chain== use karke **non-contiguous memory regions** se/mein data transfer kar sakte hain.
**Problem:** Network packet ka header ek buffer mein hai, payload doosre mein. Simple DMA ke liye beech mein CPU intervention ke saath do alag transfers chahiye.
**Solution:** Descriptor list memory mein:
```c
struct dma_descriptor {
uint32_t source_addr;
uint32_t dest_addr;
uint16_t byte_count;
uint16_t flags; // Last descriptor bit, interrupt bit
uint32_t next_desc; // Pointer to next descriptor (linked list)
};
```
> [!formula] Scatter-Gather Operation
> 1. CPU pehle descriptor ka address DMA controller mein likhta hai
> 2. DMA memory se descriptor fetch karta hai (additional bus read)
> 3. DMA woh transfer perform karta hai jo descriptor mein describe hai
> 4. Agar last descriptor nahi hai, DMA `next_desc` se agla descriptor fetch karta hai
> 5. Jab tak last descriptor flag set na ho, repeat
**Overhead analysis:**
- Har descriptor ~4 cycles add karta hai (memory read + parse)
- Tradeoff: Flexibility vs. throughput
- Network packets ke liye optimal (bahut saare chhote, scattered buffers)
> [!example] Scatter-Gather Example
> Network packet transmit karo: 0x2000 pe 14-byte Ethernet header, 0x5000 pe 1500-byte payload
Descriptor chain:
```
Desc1: SAR=0x2000, DAR=NIC_TX, BCR=14, next=0x3000
Desc2: SAR=0x5000, DAR=NIC_TX, BCR=1500, next=NULL last=1
```
DMA controller dono transfers **bina CPU intervention ke** perform karta hai, NIC ko contiguous 1514-byte stream dikhta hai.
## DMA aur Caches
> [!mistake] Cache Coherency Problem
**Galti:** DMA ke memory mein data write karne ke baad, CPU fresh DMA data ki jagah purana cached data read karta hai.
**Ye sahi kyun lagta hai:** "Memory mein data hai, CPU memory read karta hai, kaam ho jaana chahiye."
**Reality:** CPU data cache karta hai. Jab DMA memory address 0x4000 mein write karta hai, CPU ke cache mein 0x4000 pe purana value hota hai. CPU cache read karta hai (fast) memory ki jagah (slow) → stale data.
> [!formula] Cache Coherency Solutions
**1. Software Cache Management:**
```
DMA ke memory mein write se pehle:
CPU destination region cover karne wali cache lines invalidate karta hai
Kyun? Ensure karo CPU stale cached data nahi padhega
DMA ke memory se read ke baad:
CPU source region cover karne wali cache lines flush (writeback) karta hai
Kyun? Ensure karo DMA ko latest CPU-written data mile
```
**2. Hardware Cache Coherency (Cache-coherent DMA):**
- DMA controller cache coherency interconnect se connect hota hai (jaise, ARM ACE, Intel QPI)
- DMA write → CPU caches snoop karta hai, matching lines automatically invalidate karta hai
- Software ke liye transparent lekin hardware cost badhta hai
**3. Non-cacheable Memory Regions:**
- DMA buffers ko page tables mein non-cacheable mark karo
- Saare accesses cache bypass karte hain → hamesha coherent
- Performance penalty: CPU har access pe memory latency bharta hai
## Performance Analysis
> [!formula] DMA Efficiency Metric
$$\text{Efficiency} = \frac{\text{Useful data transferred}}{\text{Total bus cycles consumed}}$$
> [!example] Efficiency Comparison
> Memory regions ke beech 16 KB transfer karo:
**CPU copy (memcpy):**
- Load word: 1 cycle (agar cache hit, warna +10 for memory)
- Store word: 1 cycle
- Per word: ~5 cycles average (loop overhead including)
- Total: $\frac{16384}{4} \times 5 = 20{,}480$ cycles
- CPU 100% busy
- Efficiency: $\frac{4096 \text{ words}}{20{,}480} = 0.20$ (20%)
**DMA burst:**
- Setup: 10 cycles
- Transfer: 4096 words × 1 cycle = 4096 cycles
- Total: 4106 cycles
- CPU cycle 10 ke baad free
- Efficiency: $\frac{4096}{4106} \approx 0.998$ (99.8%)
**Speedup:** $\frac{20{,}480}{4106} \approx 5\times$ faster, **aur** CPU doosre kaam ke liye free.
## Multi-Channel DMA Controllers
Modern DMA controllers mein **multiple independent channels** hote hain (typically 4-32).
> [!formula] Channel Scheduling
> Har channel ke alag registers hote hain (SAR, DAR, BCR, CSR). Hardware active channels ke beech arbitrate karta hai:
$$\text{If multiple channels active} \rightarrow \text{Round-robin or priority-based scheduling}$$
**Multiple channels kyun?**
- Simultaneous transfers: SD → Memory jabki Memory → Network
- Head-of-line blocking se bachao: Chota transfer lamba transfer ka wait nahi karta
- Har channel ke liye alag interrupt handlers
> [!example] Dual-Channel Scenario
> - Channel 0: Disk read, 1 MB transfer (cycle-steal mode mein 1000 μs leta hai)
> - Channel 1: UART receive, 10 bytes (10 μs leta hai)
Single channel ke saath: UART 1000 μs wait karta hai → buffer overrun
Dual channel ke saath: UART Channel 1 use karta hai, parallel mein 10 μs mein complete
## Common Mistakes
> [!mistake] Caches ko Flush/Invalidate karna Bhool Jana
**Galti:** DMA transfer setup karo, start karo, CPU turant destination buffer read kare → garbage dikhta hai.
**Ye sahi kyun lagta hai:** "Maine DMA program kiya, data wahan hona chahiye."
**Steel-man:** Tum sahi ho ki DMA **zaroor** memory mein data likhega. Issue **timing** aur **cache** ka hai:
1. DMA time leta hai (microseconds to milliseconds)
2. CPU cache mein destination address pe purana data ho sakta hai
3. CPU DMA ke memory mein likhna finish karne se pehle cache read kar leta hai
**Fix:**
```c
// DMA se pehle
dma_setup(channel, src dst, size);
cache_invalidate(dst, size); // Cache se stale dst data hatao
dma_start(channel);
// Completion ka wait karo
while (!dma_done(channel)); // Ya interrupt use karo
// Ab dst read karo - cache miss memory se fresh DMA data force karta hai
process_buffer(dst, size);
```
> [!mistake] Alignment Check Na Karna
**Galti:** SAR=0x1001, width=32-bit ke saath DMA transfer → system crash ya data corruption.
**Ye sahi kyun lagta hai:** "Memory bas bytes hain, koi bhi address kaam karega."
**Steel-man:** Tum sahi ho ki memory byte-addressable hai. Lekin DMA **hardware** ko aksar word transfers ke liye **word-aligned** addresses chahiye:
- 32-bit transfer → address 4 ka multiple hona chahiye (bottom 2 bits = 00)
- 16-bit transfer → address 2 ka multiple hona chahiye (bottom bit = 0)
**Kyun?** Hardware simplification: 32-bit datapath address bits [31:2] se connect hota hai, [31:0] se nahi. Unaligned access ke liye extra logic chahiye (shift, merge) → zyaadatar DMA controllers ise forbid karte hain.
**Fix:**
```c
// Galat
uint8_t buffer[1024];
dma_setup(src, buffer+1, 1000, WIDTH_32BIT); // buffer+1 unaligned!
// Sahi
uint8_t buffer[1024] __attribute__((aligned(4))); // Alignment force karo
dma_setup(src, buffer, 1000, WIDTH_32BIT); // Aligned
```
> [!mistake] Fixed-Mode DAR ke saath Buffer Overrun
**Galti:** Peripheral fixed SAR address se read karta hai, lekin BCR FIFO depth se zyaada → DMA same stale data baar baar read karta hai.
**Ye sahi kyun lagta hai:** "Peripheral FIFO ka single address hai, toh fixed mode use karo."
**Steel-man:** Correct hai ki peripheral FIFO ka single address hota hai. Lekin tumne assume kiya ki FIFO mein hamesha data hai. Reality:
- FIFO ki finite depth hoti hai (jaise, 16 entries)
- Agar DMA peripheral se zyaada fast read kare → underrun
- DMA same purana value 16 baar read karta hai, phir garbage
**Fix:** **Flow control** use karo (aka **DMA handshaking**):
- Peripheral DREQ (DMA request) signal assert karta hai jab FIFO mein data ho
- DMA tabhi transfer karta hai jab DREQ=1 ho
- FIFO khaali hone pe peripheral DREQ de-assert karta hai
- DMA automatically pause ho jaata hai
```
BCR = 1000, FIFO depth = 16
DMA 16 bytes read karta hai → FIFO khaali → DREQ=0 → DMA pause
Peripheral FIFO refill karta hai → DREQ=1 → DMA resume
Jab tak BCR = 0 nahi ho, repeat
```
## Advanced: DMA aur Virtual Memory
> [!formula] DMA with MMU
**Problem:** CPU **virtual addresses** use karta hai, lekin DMA hardware **physical addresses** use karta hai.
**Example:** Virtual 0xC000_0000 pe CPU buffer physical 0x010_0000 map hota hai (MMU translation).
**Solution 1: Physical addressing (sabse common):**
1. CPU buffer allocate karta hai, virtual address milta hai
2. CPU OS se physical address query karta hai (page table lookup)
3. CPU DMA ko **physical** address se program karta hai
4. DMA physical memory directly access karta hai (MMU bypass karta hai)
**Solution 2: IOMMU (advanced systems):**
- ==IOMMU== (Input/Output Memory Management Unit): DMA devices ke liye MMU
- DMA device virtual addresses use karta hai → IOMMU physical mein translate karta hai
- DMA ko descriptor chains ke bina scattered physical pages pe enable karta hai
- Security: DMA ko unauthorized memory access karne se rokta hai
## Summary
> [!recall]- Ek 12 saal ke bachhe ko explain karo
> Socho tumhari mummy tumse kehti hain garage se attic mein 100 boxes le jaao. Tum khud har box carry kar sakte ho (ye CPU ki tarah hai jo data byte-by-byte move karta hai), lekin isse saara din lag jaayega aur tum homework nahi kar paoge.
Iski jagah, tumhari mummy ek moving crew hire karti hain (ye DMA controller hai). Tum unhe ek baar bata do: "100 boxes garage se attic le jaao." Phir tum apna homework karne jaate ho jabki woh kaam karte hain. Jab finish karte hain, woh ek ghanti bajaate hain (interrupt) tumhe batane ke liye.
Crew tumse utni smart nahi hai—woh sirf seedhi line mein boxes move kar sakti hai, aur tumhe exact plan set up karna hota hai. Lekin woh us ek kaam mein bahut fast hain, aur sabse acha part ye hai ki tum dusre kaam kar sakte ho jabki woh kaam karte hain. Isliye computers DMA use karte hain: CPU bahut valuable hai sirf simple data copying mein waste karne ke liye.
> [!mnemonic] DMA Register Mnemonic
> **S**ally **D**rives **B**ig **C**ars
> - **S**AR: Source Address Register
> - **D**AR: Destination Address Register
> - **B**CR: Byte Count Register
> - **C**SR: Control/Status Register
## Connections
- [[Bus Architecture]] - DMA bus master ki tarah act karta hai, arbitration chahiye
- [[Interrupts]] - DMA completion notification mechanism
- [[Cache Coherency]] - CPU caches ke saath critical interaction
- [[Memory-Mapped IO]] - DMA peripheral registers read/write karta hai
- [[PCIe]] - Modern DMA-capable interconnect
- [[UART]] - DMA use karne wala example peripheral
- [[SDRAM Controllers]] - DMA ke liye memory destination/source
- [[ARM AMBA AXI]] - Bus protocol jo advanced DMA features support karta hai
---
#flashcards/hardware
DMA ka primary purpose kya hai? :: Memory aur peripherals ke beech (ya memory-to-memory) bina continuous CPU intervention ke data transfer karna, taaki CPU doosre tasks ke liye free ho.
DMA controller mein chaar essential registers kaun se hain? ::: Source Address Register (SAR), Destination Address Register (DAR), Byte Count Register (BCR), aur Control/Status Register (CSR).
Burst mode aur cycle-stealing mode mein kya farq hai? ::: Burst mode bus acquire karta hai aur poore transfer ke liye hold karta hai (high throughput, CPU starvation), jabki cycle-stealing har transfer ke baad bus release karta hai (lower throughput, better CPU responsiveness).
Scatter-gather DMA kya hai? ::: DMA technique jo descriptor chain use karke ek single operation mein bina CPU intervention ke non-contiguous memory regions se/mein data transfer karta hai.
DMA buffers cache-coherent kyun hone chahiye? ::: Kyunki DMA directly memory mein write karta hai jabki CPU cache se read kar sakta hai; coherency ke bina, CPU fresh DMA data ki jagah stale cached data read karta hai.
DMA write ke liye cache coherency solution kya hai? ::: DMA write se pehle, CPU destination region cover karne wali cache lines invalidate karta hai taaki baad mein CPU reads memory se fresh data fetch karein.
DMA controllers ko aligned addresses kyun chahiye? ::: Hardware simplification: word-width transfers aligned address bits se connect hote hain; unaligned access ke liye extra shift/merge logic chahiye jo zyaadatar DMA hardware mein nahi hota.
IOMMU kya hai? ::: Input/Output Memory Management Unit; DMA devices ke liye address translation provide karta hai, unhe virtual addresses use karne deta hai aur memory access restrict karke security improve karta hai.
DMA flow control (DREQ) kaun si problem solve karta hai? ::: Buffer overrun/underrun se bachata hai, peripheral ek request signal assert karta hai tabhi jab data available ho, jab peripheral ready nahi hota toh DMA pause ho jaata hai.
Efficiency calculate karo: DMA 8 KB burst mode mein transfer karta hai 5-cycle setup aur 1 cycle per word (32-bit) ke saath. :: Transfers = 8192/4 = 2048, Total cycles = 5 + 2048 = 2053, Efficiency = 2048/2053 ≈ 99.76%
## 🖼️ Concept Map
```mermaid
flowchart TD
PIO[Programmed I/O] -->|wastes CPU cycles| PROB[CPU Bottleneck Problem]
PROB -->|motivates| DMA[Direct Memory Access]
DMA -->|orchestrated by| DMAC[DMA Controller]
DMAC -->|acts as| BM[Bus Master]
DMAC -->|frees CPU for| WORK[Concurrent Useful Work]
DMAC -->|signals done via| IRQ[Completion Interrupt]
DMAC -->|contains registers| REGS[Channel Registers]
REGS -->|read source| SAR[Source Address Reg]
REGS -->|write dest| DAR[Destination Address Reg]
REGS -->|remaining bytes| BCR[Byte Count Reg]
REGS -->|mode bits| CSR[Control/Status Reg]
CSR -->|controls| MODE[Direction, Width, Increment]
```