6.2.10 · D5 · HinglishGPU Architecture
Question bank — Occupancy and latency hiding
6.2.10 · D5· Hardware › GPU Architecture › Occupancy and latency hiding
Shuru karne se pehle, teen plain-word anchors taaki koi bhi term use hone se pehle clearly define ho:
- Warp 32 threads ka ek group hai jo saath chalta hai, same instruction ko lockstep mein execute karta hai.
- Occupancy ek ratio hai: ek Streaming Multiprocessor par actually resident warps ko us SM ke maximum possible warps se divide karo. Dekho 6.2.1-SM-Architecture.
- Latency hiding ka matlab hai ki SM kisi slow operation ke dauran kabhi idle nahi baithta, kyunki woh kisi doosre ready warp par switch kar leta hai. Woh scheduler jo warp pick karta hai usse 6.2.8-Warp-Scheduling mein cover kiya gaya hai.
True or false — justify karo
True or false: Occupancy ko double karne se hamesha throughput double hoti hai.
False — throughput vs. occupancy ek saturating curve hai. Jab enough warps longest latency ko cover karne ke liye aa jaate hain, extra warps pool mein bekar baithe rehte hain kuch naya nahi karte, toh curve flat ho jaata hai.
True or false: SM par warps ke beech switch karna bahut idle cycles leta hai, jaise CPU context switch.
False — har warp ke registers on-chip resident rehte hain, toh scheduler bilkul agle cycle mein ek alag warp pick kar sakta hai essentially zero cost par. Yahi zero-cost switch poori latency hiding ka reason hai.
True or false: Ek akela warp apne dum par 400 cycles ki memory latency ko fully hide kar sakta hai.
False — ek warp ek waqt mein ek memory instruction issue karta hai aur phir apne result ka wait karta hai. Latency hide karne ke liye bahut saare warps in-flight chahiye taaki SM ke paas hamesha kuch aur ready ho.
True or false: 100% occupancy har kernel ka design target hai.
False — asli target zero scheduling stalls hai. Agar 32 warps pehle se saari latency hide kar rahe hain, toh 64 karna sirf register aur cache pressure add karta hai bina kisi gain ke.
True or false: Occupancy hardware ki ek property hai, kisi given GPU ke liye fixed hoti hai.
False — yeh us kernel ki property hai jo hardware par run ho raha hai. Wahi GPU alag occupancy deta hai depending on registers/thread, shared memory/block, aur block size.
True or false: Ek compute-bound kernel occupancy max out karne se benefit karta hai.
Usually false — compute-bound code ALU throughput se limited hota hai, ready warp dhundhne se nahi. Yeh apni short latencies ko thodi si warps aur instruction-level parallelism se hide kar leta hai, toh extra warps registers waste karte hain.
True or false: Active warps ki sankhya badhane se kisi bhi single memory load ki latency kam hoti hai.
False — ek load ki intrinsic latency unchanged rehti hai. Zyada warps aapko bahut saari esi latencies ko overlap karne deti hain taaki SM busy rahe; individual load utna hi slow hai.
True or false: Agar kernel koi shared memory use nahi karta, toh shared memory kabhi uski occupancy limit nahi kar sakti.
True — jab per-block shared memory zero ho, toh shared-memory term ek binding constraint nahi hai, toh occupancy registers ya block/warp hardware caps se set hoti hai.
True or false: Coalesced memory access kernel ki occupancy change karta hai.
False — Coalescing yeh change karta hai ki memory system requests ko kitni efficiently serve karta hai, resident warps ki sankhya nahi. Yeh us latency ko affect karta hai jo aapko hide karni hai, warps ki sankhya ko nahi jo usse hide kar sakti hain.
Error dhundho
"Mera kernel 128 registers/thread use karta hai aur maine launch config mein occupancy 100% set ki — ho gaya."
Aap occupancy set nahi kar sakte; launch config plus per-thread resource use usse determine karta hai. 65,536-reg SM par 128 regs/thread par sirf 16 warps fit hote hain, occupancy 25% par cap ho jaati hai intent se koi fark nahi padta.
"Occupancy = active threads ÷ max threads, toh main directly threads count karta hoon."
Jo unit matter karti hai woh warp hai, kyunki scheduler per cycle ek warp-instruction issue karta hai. Occupancy active warps over max warps hai; threads count tab hi agree karta hai jab sab kuch evenly 32 mein divide ho.
"Store latency ~400 cycles hai, toh mujhe apne critical path mein per-thread 400 aur cycles add karne padte hain."
Global stores asynchronously retire hote hain — yeh buffer mein jaate hain aur background mein drain hote hain. Store ki latency normally critical path par nahi baithti; sirf woh load jiske result ki aapko actually zaroorat hai woh critical path par hota hai.
"Higher occupancy ne register spills cause kiye, toh occupancy buri hai."
Ulta hai — aapne registers/thread kam karke occupancy badhaayi, jisse live data local memory mein spill hone laga. Spilling hurt karti hai, occupancy khud nahi; aapne register room ko warp count ke liye bahut aggressively trade kiya.
"Mere paas 4 schedulers hain, toh mujhe single-scheduler estimate se 4× zyada warps chahiye."
Ulti direction hai — 4 schedulers consecutive cycles mein alag warps se issue karke concurrency supply karte hain, toh naive single-scheduler warp count overshoot karta hai. Real kernels single-scheduler formula se kaafi kam warps mein latency hide kar lete hain.
"Meri occupancy 50% hai lekin performance theek hai, toh profiler galat hai."
50% often enough hoti hai. Agar woh warps pehle se load latency cover kar rahe hain, toh aap curve ke plateau par hain; profiler sahi hai aur 50% simply sufficient hai yahaan.
Why questions
Warp exactly 32 threads ka kyun hota hai, 16 ya 64 kyun nahi?
32 lanes hardware cost aur parallelism ke beech balance banata hai, aur yeh memory hardware se match karta hai — ek 128-byte cache line exactly 32 four-byte floats hold karta hai, toh ek coalesced warp access ek line par map hota hai.
GPU single-operation latency minimize karne ki bajaye throughput kyun chase karta hai jaise CPU karta hai?
CPU transistors caches aur out-of-order logic par spend karta hai taaki ek thread fast ho. GPU unhe thousands of resident threads par spend karta hai, toh yeh high latency tolerate karta hai hamesha doosra kaam rakh kar — yeh strategy Little's Law quantify karta hai.
Occupancy compute karte waqt hum register, shared-memory, aur block limits ka minimum kyun lete hain?
Jo bhi resource pehle khatam hota hai woh cap karta hai ki kitne warps fit hote hain. Yeh ek bottleneck hai: sabse scarce resource decide karta hai, toh sabse choti limit win karti hai.
Ek memory-bound kernel utne kam occupancy mein kyun tolerate kar sakta hai jitna aap darenge?
Iske warps loads issue karte hain jo memory system parallel mein serve karta hai, toh even 16–32 warps enough requests in-flight daal dete hain taaki SM busy rahe jabki har load ke saikdon cycles elapse hote hain.
Register spills sirf kam warps hone se zyada kyun hurt karte hain?
Spilling ek thread ko serialize karta hai — usse apna khud ka data local memory se load/store karna padta hai continue karne se pehle, har warp ke andar latency add karta hai. Low occupancy ka matlab sirf kam warps hai, lekin har surviving warp phir bhi full speed par chalta hai.
100% occupancy us kernel ki help kyun nahi karta jo pehle se koi scheduling bubbles nahi rakhta?
Agar scheduler hamesha ek ready warp dhundh leta hai, toh fill karne ke liye koi idle cycle hi nahi bachi. Extra warps hide karne ke liye kuch nahi add karte aur sirf registers aur cache consume karte hain, kabhi kabhi cheezein worse kar dete hain.
Bytes ke per arithmetic badhana (arithmetic intensity) occupancy par pressure kyun kam karta hai?
Har memory access par zyada compute ka matlab hai ki har load ki latency naturally real kaam se overlap hoti hai, kernel ko roofline ke compute-bound side ki taraf move karta hai jahaan kam warps sufficient hote hain.
Edge cases
Ek SM par exactly ek block of 32 threads ke saath launch kiye gaye kernel ki occupancy kya hai jo 64 warps hold karta hai?
64 mein se ek warp resident → approximately 1.6% occupancy. Essentially koi latency hiding nahi hai: jab woh akela warp stall karta hai, SM idle ho jaata hai.
Agar do kernels mein se har ek SM ki shared memory ka 50% chahiye, kya woh ek SM par simultaneously share kar sakte hain?
Sirf tab jab unki combined resource demand (shared memory, registers, warp slots) SM ke totals mein fit ho. Concurrent-kernel residency same min-of-resources rule se bounded hai, loosely add kiye gaye occupancy percentages se nahi.
Ek block ne SM ke total se zyada shared memory request ki — occupancy ka kya hoga?
Kernel launch hi nahi ho sakta; zero blocks fit hote hain, toh occupancy undefined/zero hai. Resource ceiling ek hard wall hai, sirf throttle nahi.
Ek kernel 25% occupancy par perfectly latency-hidden hai — kya isko 50% tak raise karna kabhi harmful ho sakta hai?
Yeh ho sakta hai. Warps double karne ke liye registers/thread halving karna spills force kar sakta hai, aur zyada resident data L1/cache ko thrash kar sakta hai — toh 50% already-sufficient 25% se slower run kar sakta hai.
Jab pool mein har warp ek hi dependent load par same instant mein wait kar raha ho toh latency hiding ka kya hoga?
Issue karne ke liye kuch ready nahi hai, toh high occupancy ke bawajood SM stall karta hai. High warp count tab hi help karta hai jab warps alag alag times par ready hon — occupancy necessary hai par sufficient nahi.
Agar ek Tensor-Core-heavy kernel compute-bound hai, kya occupancy phir bhi matter karti hai?
Bahut kam — Tensor Cores ALU throughput par saturate hote hain, toh ek modest warp count unhe fed rakhta hai. Jab matrix pipelines full ho jaati hain toh extra warps rarely speed add karte hain.
Recall Fast self-check
One-warp SM ⇒ ?occupancy aur ?hiding ::: ~1.6% occupancy aur effectively koi latency hiding nahi — SM har stall par idle ho jaata hai. Store latency critical path par? ::: Nahi — stores asynchronously buffers ke through retire hote hain; sirf needed load count karta hai. Occupancy formula resources ke across konsa combining rule use karta hai? ::: Minimum — sabse scarce resource resident warps ko cap karta hai.