Question bank — Flynn's taxonomy (SISD - SIMD - MIMD)

Ek GPU ek MIMD machine hai kyunki uske paas hazaaron cores hain. ::: False. Hazaaron cores ka matlab hazaaron instruction streams nahi hota; ek GPU ek instruction ko ek group of lanes mein ek saath broadcast karta hai (NVIDIA aise lock-stepped group of 32 lanes ko warp kehta hai), toh us group ke andar yeh SIMD (data-parallel) hai, MIMD nahi. SISD hardware kabhi ek se zyada program nahi chala sakta. ::: False. Ek single SISD core time-slices karta hai: OS programs ke beech rapidly switch karta rehta hai. Ek moment mein sirf ek instruction execute hoti hai, toh yeh phir bhi Single-Instruction hai — concurrency scheduling ka ek illusion hai, real parallelism nahi. SIMD hamesha N lanes ke saath exactly N× speedup deta hai. ::: False. N× ek ideal ceiling hai. Load/store overhead, misalignment, leftover elements jab array length N ka multiple nahi hoti, aur koi bhi data dependency — yeh sab milkar real speedup ko typically 2–4× tak kheench laate hain. MIMD hardware woh sab kar sakta hai jo SIMD kar sakta hai. ::: Capability mein True, lekin efficiency mein nahi. Har MIMD core same instruction alag-alag data par chalate hue SIMD ko mimic karta hai, phir bhi yeh N separate fetch/decode costs pay karta hai ek broadcast ki jagah — toh yeh woh instruction bandwidth waste karta hai jo SIMD bachata hai. Ek dual-core laptop ek single-threaded program chalate waqt us program ke liye SISD ki tarah behave karta hai. ::: True. Agar program kabhi second instruction stream spawn nahi karta, toh sirf ek core use drive karta hai: apne data par ek time mein ek instruction stream — yeh SISD behaviour hai chahe kitne bhi cores idle baithe hon. Classification hardware par nahi, software par depend karti hai. ::: Aadha False. Flynn hardware ki capability classify karta hai (kitne instruction/data streams woh chala sakta hai). Lekin woh capability use hoti hai ya nahi yeh software par depend karta hai — ek MIMD chip serial code chalate waqt SISD performance deta hai.

"MISD sabse common category hai kyunki pipelining har jagah hai." ::: Galat. MISD (kai instructions, ek data element) sabse rare, near-theoretical box hai; pipelining MISD nahi hai kyunki ek pipeline alag-alag data ka ek stream process karta hai, ek datum ko kai independent instruction streams ke through nahi. "Ek instruction ko 4 units mein broadcast karne ka matlab control unit 4× zyada mehnat karta hai." ::: Galat — woh kam kaam karta hai. SIMD ka poora point yahi hai ki fetch/decode ek baar hota hai aur saare 4 lanes ko drive karta hai, toh per data element control-unit effort ghadta hai, badhta nahi. "SIMD mein chaar additions chaar cycles mein khatam hote hain, ek lane per cycle." ::: Galat. Lanes ek hi cycle mein lockstep mein chalte hain, ek ke baad ek nahi. Yahi simultaneity hai jo SIMD ko SISD loop se alag karti hai. "Amdahl's Law kehta hai ki enough cores ke saath speedup unlimited hai." ::: Galat. Jaise cores ki sankhya $N$ bina had ke badhti hai, $S(N)$ approach karta hai $\frac{1}{1-P}$ (seedhe alfazon mein: 1 divided by the serial fraction), ek hard ceiling. Ek program jo 10% serial hai woh kabhi 10× speedup exceed nahi kar sakta, chahe cores kitne bhi hon. "SIMD ko apne lanes ke beech cache coherence ki zaroorat hai." ::: Galat. Cache coherence ek MIMD shared-memory problem hai, jahan independent cores same address par likh sakte hain. SIMD lanes ek control unit dwara lockstep mein drive hoti hain aur us tarah independently shared state nahi likhtin. "Distributed-memory MIMD cores ek RAM share karte hain, toh message passing optional hai." ::: Galat. Distributed memory ka matlab hai har core ke paas private RAM hai; koi shared address space nahi hai, toh explicit message passing (jaise MPI) required hai, optional nahi.

Flynn ne sirf "parallel vs not" ki jagah do axes kyun use kiye? ::: Kyunki parallelism do independent dimensions mein ho sakti hai — same instruction across many data (data-level) versus kai instructions independently chal rahi hain (instruction-level). Ek binary label GPU aur multicore CPU mein fark nahi kar sakta; do axes kar sakte hain. SIMD images aur audio ke liye ideal kyun hai lekin web server ke liye poor kyun hai? ::: Images/audio millions of uniform elements par same operation apply karte hain (data parallelism), jise SIMD ka single broadcast perfectly exploit karta hai. Ek web server alag-alag algorithms per request chalata hai (task parallelism), toh broadcast karne ke liye koi common instruction nahi hoti. SISD loop sum += array[i] ko parallelize kyun nahi kar sakta? ::: Kyunki har iteration pichle wali ke likhe hue sum ko padhti hai — ek data dependency. Element order matter karta hai, toh additions result change kiye bina simultaneously nahi ho sakti. SIMD instruction bandwidth kyun kam karta hai? ::: Ek instruction fetch aur decode hoti hai, phir N lanes mein reuse hoti hai. Toh N data operations ki cost sirf ek instruction transfer from memory hoti hai, fetch/decode traffic ko N factor se kaat deta hai. Cache coherence ek MIMD-specific headache kyun hai? ::: Sirf MIMD ke paas multiple independent control units hain jo shared memory mein likhte hain. Agar core 1 apne cache mein X=5 likhta hai, toh core 2 ko woh dekhna zaroori hai — ek coordination problem jo SISD (ek writer) aur SIMD (ek instruction stream) ko simply nahi hoti.

MISD kya hai, aur yeh nearly empty kyun hai? ::: MISD = Multiple Instruction, Single Data: kai alag instruction streams sab ek hi same data element ko process kar rahe hain. Yeh logically chautha box hai lekin iske paas almost koi real machines nahi hain; sabse kareeb niche fault-tolerant redundancy hai (kai units ek datum check kar rahe hain). SIMD mein kya hota hai jab tumhare array mein 10 elements hain lekin sirf 8 lanes hain? ::: Tumhe do passes chahiye: ek full 8-wide operation aur ek partial pass jo baaki 2 handle karta hai. Tail lanes waste karta hai (masking ya scalar cleanup), toh effective speedup ideal N× se neeche aa jaata hai. Agar $P$ (parallel fraction) = 0 hai, toh Amdahl's Law kya predict karta hai? ::: $S(N)=\frac{1}{(1-0)+0}=1$ (seedhe alfazon mein: 1 / (1 + 0) = 1). Bilkul bhi speedup nahi — ek purely serial program ko extra cores se kuch faayda nahi, yahi law ka poora cautionary point hai. Agar $P=1$ (perfectly parallel) hai, toh N cores par speedup kya hai? ::: $S(N)=\frac{1}{0+1/N}=N$ (seedhe alfazon mein: 1 / (1/N) = N) — ideal linear speedup. Yeh unreachable best case hai, kyunki real code mein hamesha kuch serial setup, I/O, ya synchronisation hoti hai. Kya ek single-core CPU jo internal pipeline use karta hai phir bhi SISD hai? ::: Haan. Ek pipeline alag-alag instructions ke stages ko overlap karta hai, lekin Flynn ke viewpoint se abhi bhi ek instruction stream hai jo ek data stream feed kar rahi hai. Pipelining instruction-level overlap hai, naya stream nahi, toh SISD label remain karta hai. Kya same physical chip ek moment mein SIMD aur doosre mein MIMD ki tarah act kar sakta hai? ::: Haan. Ek modern GPU ya CPU alag cores ko independent kernels par chala sakta hai (MIMD) jabki har core internally apni lanes mein ek instruction broadcast karta hai (SIMD). Flynn ke boxes execution ke modes describe karte hain, aur hardware unke beech switch kar sakta hai. Ek modern multicore CPU jisme SIMD vector units hain (jaise AVX) kahan fit hota hai? ::: Core level par yeh MIMD hai (har core ka apna instruction stream hai) aur har core ke andar yeh SIMD hai (AVX ek instruction ko ek packed vector par apply karta hai). Real chips hybrid hote hain, toh Flynn labels ek dominant mode describe karta hai, exclusive nahi.