Write-through vs write-back — Hinglish notes

5.4.6 · Hardware › Memory Hierarchy & Caches

The Write Problem

Jab ek CPU kisi cached address par store instruction perform karta hai, toh hume decide karna padta hai kab main memory ko update karein. Cache aur memory dono data ki copies hold karte hain—ye inconsistent ho sakti hain.

Ye kyun zaroori hai: Reads easy hain (cache hit = fast, cache miss = memory se fetch). Lekin writes ek dirty state create karte hain jahan cache ke paas memory se zyada naya data hota hai.

Write-Through Policy

Ye Kaise Kaam Karta Hai

CPU STORE instruction issue karta hai
Cache apni line update karta hai (agar hit ho)
Saath hi saath, store memory ko forward ho jaata hai
Write tab complete hota hai jab memory acknowledge kare

Write time ki derivation: $T_{write-through} = T_{cache-write} + T_{memory-write}$

Kyunki $T_{memory-write} ≫ T_{cache-write}$ hai (memory ~100 ns, cache ~1 ns), memory access dominate karta hai: $T_{write-through} \approx T_{memory-write}$

Ye step kyun? Cache write itna fast hai memory ke comparison mein ki ye total time mein negligible ho jaata hai.

Worked example Write-Through Example

Initial state:
Cache[0x100] = 42
Memory[0x100] = 42

CPU: STORE 0x100, 99
Step 1: Cache[0x100] ← 99    (1 ns)
Step 2: Memory[0x100] ← 99   (100 ns)
Total time: 101 ns
After: Cache[0x100] = 99, Memory[0x100] = 99 ✓ consistent

Ye step kyun? Har write CPU ko puri memory latency ke liye stall karta hai. Koi dirty data exist nahi karta.

Write Buffer Optimization

Memory latency ko hide karne ke liye, modern write-through caches ek write buffer use karte hain:

Derivation:

CPU cache + buffer mein write karta hai (1-2 ns)
Buffer asynchronously memory mein drain hota hai
CPU continue karta hai agar buffer full na ho

Effective write time: $T_{effective} = T_{cache} + T_{buffer-insert}$

Buffer N writes absorb kar sakta hai stall hone se pehle (typical N=4-8). Agar writes buffer drain se zyada fast aayein: $Stall occurs when R_{write} > \frac{N}{T _{memory-write}}$

Ye step kyun? Buffer CPU speed ko memory speed se decouple karta hai, lekin sirf apni depth tak.

Write-Back Policy

Ye Kaise Kaam Karta Hai

CPU STORE instruction issue karta hai
Cache apni line update karta hai aur ==dirty bit = 1== set karta hai
Write immediately complete hota hai (koi memory access nahi)
Eviction par: Agar dirty bit = 1 hai, poori line memory mein write karo; warna discard karo

Write time ki derivation: $T_{write-back} = T_{cache-write} (assuming hit)$

Kyunki cache write ~1 ns aur memory write ~100 ns hai: $Speedup = \frac{T _{write-through}}{T _{write-back}} = \frac{100}{1} = 100 \times$

Ye step kyun? Humne memory writes ko critical path se hata diya hai unhe defer karke.

The Eviction Cost

Jab ek dirty line evict hoti hai (jaise conflict miss ki wajah se), toh hume:

Dirty line ko memory mein likhna padta hai (1 cache line = typically 64 bytes)
Phir nyi line fetch karni padti hai

$T_{miss-with-dirtyevict} = T_{writeback-old} + T_{fetch-new} = 2 \times T_{memory-access}$

Ye step kyun? Hum double memory latency pay karte hain: ek write, ek read. Lekin ye sirf dirty evictions wale misses par hota hai.

Worked example Write-Back Example

Initial:
Cache[0x100] = 42, Dirty=0
Memory[0x100] = 42

CPU: STORE 0x100, 99

Step 1: Cache[0x100] ← 99, Dirty ← 1   (1 ns)
Done! (Memory abhi bhi 42 hai)

Later: Line 0x100 evicted (conflict miss)
Step 2: Memory[0x100] ← 99              (100 ns)
Step 3: Fetch new line                (100 ns)
Total write time: 1 ns
Eviction cost: 200 ns (amortized over many writes)

Ye step kyun? Humne immediate consistency ko speed ke liye trade kiya. Same line par multiple writes sirf 1 ns each cost karti hain; memory write eviction par ek baar hoti hai.

Comparative Analysis

Aspect	Write-Through	Write-Back
Write Latency	High (~100 ns)	Low (~1 ns)
Memory Traffic	Har write par	Sirf evictions par
Consistency	Hamesha synchronized	Delayed (dirty data)
Read Miss Penalty	$T_{memory}$	$2 \times T_{memory}$ (agar dirty ho)
Complexity	Simple	Dirty bit, writeback logic chahiye
Bus Utilization	High	Low
Multi-core Coherence	Easier (memory up-to-date)	Harder (cache-to-cache transfers chahiye)

Bus utilization ki derivation:

Write-through: Har write bus use karta hai. $Bus Writes_{WT} = Store Instructions$

Write-back: Sirf evictions bus use karti hain. $Bus Writes_{WB} = Store Instructions \times Miss Rate \times P_{dirty}$

Typical values: Miss Rate = 5%, $P_{dirty}$ = 50% $\frac{Bus Writes _{WB}}{Bus Writes _{WT}} = 0.05 \times 0.5 = 0.025 = \frac{1}{40}$

Ye step kyun? Write-back good locality wale workloads ke liye memory traffic ~40× reduce karta hai.

Common Mistakes

Cache Write Policies Decision Tree

Write occurs
    │
    ├─ Cache Hit?
    │   ├─ Write-Through: Update cache + memory (100 ns)
    │   └─ Write-Back: Update cache + set dirty (1 ns)
    │
    └─ Cache Miss?
        ├─ Write-Allocate (modern): Fetch line, then write
        │   ├─ Write-Through: Fetch + write cache + write memory
        │   └─ Write-Back: Fetch + write cache + set dirty
        │
        └─ No-Write-Allocate (rare): Write directly to memory

Advanced Considerations

Write-Through + Write-Back Hybrid

Kuch systems selective write policies use karte hain:

Frequently accessed data (stack, heap): write-back
I/O regions, memory-mapped devices: write-through

Ye step kyun? I/O devices expect kar sakte hain ki writes immediately visible hon. Write-through ye complex coherence protocols ke bina ensure karta hai.

Multi-Level Caches

Zyaatar modern processors mein, saare cache levels (L1, L2, L3) write-back use karte hain taaki levels ke beech aur memory tak traffic minimize ho. L1 par write sirf L1 update karta hai aur uska dirty bit set karta hai; L1 eviction par dirty line L2 mein write back hoti hai, aur L2 eviction par memory mein (aur aage bhi).

$L 1 writeback on evict L 2 writeback on evict Memory$

Ye step kyun? Har level par write-back fast L1→L2 aur slow L2→Memory paths ko critical write path se door rakhta hai. Kuch designs write-through L1 backed by write-back L2 use karte hain (L1 coherence aur error recovery simplify karne ke liye), lekin ye exception hai rule nahi—saare levels par write-back modern common choice hai.

Recall Feynman: Ek 12-saal ke bachche ko samjhao

Socho tum class mein notes le rahe ho. Tumhare paas ek chhota notepad (cache) hai aur ek bada notebook (memory).

Write-through is tarah hai jaise teacher jo kuch bhi kahe, tum turant apne notepad AUR bade notebook dono mein copy karo. Isme zyada time lagta hai kyunki tum do jagah likh rahe ho, lekin tumhara bada notebook hamesha up-to-date rehta hai. Agar tumhara notepad kho jaaye, koi baat nahi—sab kuch bade notebook mein hai.

Write-back is tarah hai jaise class ke dauran notepad mein jaldi se notes scribble karo (super fast!), aur unhe din ke end mein hi bade notebook mein copy karo. Class ke dauran bahut fast, lekin agar copy karne se pehle notepad kho jaaye, toh aaj ke notes gaye! Saath hi, agar koi din ke dauran tumhara bada notebook dekhe, unhe tumhare latest notes nahi dikhenge.

"Dirty bit" is tarah hai jaise notepad ke un pages par star⭐ lagaana jo abhi copy nahi hue, taaki tumhe yaad rahe ki baad mein kaunse pages copy karne hain.

Connections

5.4.01-CacheFundamentals - Pehle cache hits/misses samjho
5.4.05-Cache-ReplacementPolicies - Eviction writebacks trigger karta hai
5.4.07-Cache-Coherence - Write policies multi-core coherence affect karti hain
5.4.08-Write-Allocate-vs-No-Write-Allocate - Write misses par kya hota hai
6.2.03-Memory-ConsistencyModels - Parallel systems mein write visibility
5.3.02-DRAM-Architecture - Memory writes slow kyun hote hain

#flashcards/hardware

Write-through cache policy :: Har write cache aur memory dono ko immediately update karta hai; hamesha synchronized lekin slower (~100 ns per write)

Write-back cache policy

Writes sirf cache ko dirty bit ke saath update karte hain; memory eviction par update hoti hai; faster (~1 ns) lekin delayed consistency

Dirty bit kya hota hai?

Ek per-line flag jo indicate karta hai ki cache line modify ho chuki hai aur memory se alag hai; eviction par writeback ki zaroorat signal karta hai

Write-through speedup with write buffer

CPU ko memory speed se decouple karta hai writes queue karke; effective agar buffer depth ≥ write burst length ho; buffer fill hone par stall hota hai

Write-back memory traffic reduction

Locality wale workloads ke liye writes ~40× reduce karta hai; sirf evictions memory mein likhti hain, har store instruction nahi

Write miss in write-back cache (write-allocate)

Pehle memory se line fetch karni padti hai (~T_memory), phir cache mein write, plus writeback agar evicted line dirty thi; ~100–200 ns cost even in write-back

Write-through kab jeetata hai?

Write-once patterns with no temporal locality; streaming writes jahan write-back koi amortization offer nahi karta; I/O regions jahan immediate visibility chahiye

Eviction cost in write-back

Dirty line eviction 2× memory latency cost karta hai (writeback old + fetch new); same line par bahut saari writes mein amortized

Dirty bit per line kyun, per byte nahi?

Memory writes line-granular hoti hain (64B bursts); per-byte tracking hardware mein bahut expensive hai; koi bhi byte dirty ho toh poori line write back hoti hai

Kya modern L1 caches write-through use karte hain?

Usually nahi—zyaatar modern processors saare cache levels (L1, L2, L3) par write-back use karte hain; write-through L1 exception hai, rule nahi