5.3.11 · D3 · HinglishAdvanced Microarchitecture

Worked examplesSpeculative execution

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5.3.11 · D3 · Hardware › Advanced Microarchitecture › Speculative execution

Yeh Speculative execution ka hands-on companion hai. Parent note ne bataya tha ki speculation kya hai aur CPUs branches pe kyun gamble karte hain. Yahan hum arithmetic drill karte hain: har tarah ke branch ke liye jo ek program CPU ko de sakta hai, hum exact cycle cost compute karte hain, decide karte hain ki speculation jeetta hai ya haarta hai, aur prove karte hain.

Numbers chhhune se pehle, chaar quantities saara kaam karti hain. Har symbol ko samjhte hain.

The scenario matrix

Branches infinite varieties mein nahi aate — woh kuch behaviour classes mein aate hain. Yeh table poori list hai. Har cell ka neeche worked example hai.

Cell Case class Kya khas baat hai Example
A Correct guess () best case, penalty kabhi pay nahi Ex 1
B Single wrong guess lambi run mein ek miss zyada hits mein amortise hota hai Ex 2 (loop)
C 50/50 unpredictable () worst realistic case, gamble haar sakta hai Ex 3
D Degenerate: limiting value, penalty term vanish ho jaata hai Ex 4
E Degenerate: (hamesha galat) pathological, penalty har baar Ex 4
F Break-even point exact accuracy jahan gamble = stall Ex 5
G Real-world word problem real code mein mixed branch mix Ex 6
H Exam twist: deeper pipeline badhta hai, verdict badalta hai Ex 7
I Security cell (correctness, speed nahi) Spectre leak count, cycles nahi Ex 8

Ab har cell work karte hain.










Recall Quick self-test

Average penalty formula ::: , jahan accuracy hai aur misprediction penalty hai. Precise vs headline penalty ::: Precise ; headline worst case hai jahan branch last stage pe resolve hoti hai (). Stall cost kya set karta hai ::: Resolve stage jahan branch condition compute hoti hai; . Jaldi resolve hone waali branches pe stall karna sasta hai, late ones pe mahanga. 2-bit counter loop exit pe sirf ek baar miss kyun karta hai ::: Uski hysteresis ka matlab hai ki ek surprise nudge karta hai lekin prediction flip nahi karta, isliye ek anomaly ek miss ki cost karti hai, wo do nahi jo ek 1-bit predictor karta. Speculate-vs-stall rule ::: Speculate tabhi karo jab . Break-even accuracy for , ::: . Deeper pipeline speculation ke liye riskier kyun hai ::: Yeh worst-case increase karta hai jabki (resolve stage se set hota hai) fixed rehta hai, isliye same miss rate zyada cycles cost karti hai aur stalling se margin shrink ho jaata hai. Kaunsa cell speed ke baare mein nahi correctness ke baare mein hai ::: Cell I — Spectre-style cache side channels; ek squashed speculative load abhi bhi cache footprint chhod jaata hai.

See also: Speculative execution · Out-of-order execution · Instruction-level parallelism (ILP) · Superscalar architecture · Pipeline hazards