Out-of-order execution: Foundations — Hinglish deep dive

5.3.2 · D1 · Hardware › Advanced Microarchitecture › Out-of-order execution

Yeh page yeh assume karta hai ki aapne kuch bhi nahi dekha. Out-of-order execution padhne se pehle, aapko us mein aane wala har word aur symbol properly samajhna hoga. Hum inhe ek ek karke build karte hain, ek se doosra.

0. "Instruction" kya hota hai? (har cheez ka atom)

Picture yeh hai: socho ek to-do list kagaz par. Har line ek kaam hai.

R1 = R2 + R3    ; line 1: add
R4 = R1 * R5    ; line 2: multiply

Yahan R1, R2, ... registers hain — CPU ke andar chote named storage boxes jo ek number rakhte hain. R1 = R2 + R3 ka matlab hai "box R2 ka number lo, box R3 ka number add karo, jawab box R1 mein rakho."

Topic ko yeh kyun chahiye: OoOE jo kuch bhi karta hai woh inhi list lines ko rearrange karna hai. Agar aap list ki picture nahi bana sakte, toh baaki kuch bhi samajh nahi aayega.

1. Program order — likha hua sequence

Picture yeh hai: to-do list ko seedha neeche padhna, order mein.

Yeh kyun matter karta hai: OoOE deliberately yeh order todta hai run karte waqt, phir uski appearance restore karta hai. Toh "program order" woh promise hai jo CPU ko rakhna hi hai, chahe secretly disobey kare.

2. Latency aur cycles — waiting hoti hi kyun hai

Neeche ki picture: ticks (columns) ki ek timeline jisme instructions boxes occupy kar rahe hain. Ek slow instruction ek lamba box hai.

Topic ko yeh kyun chahiye: agar har instruction ek jaisi choti time leti, toh reorder karne ki zyada wajah nahi hoti. Latencies ka bahut bada spread (1 cycle vs 100+) hi CPU ko motivate karta hai ki waiting ka time doosre kaam se bhare. Yahi waiting-problem aapne pehle 5.3.01-Pipelining mein dekha tha.

3. Dependency — jab ek line ko dusri ki sach mein zaroorat ho

Yahi heart hai. Ek instruction doosre par depend karti hai jab use woh value chahiye jo doosra produce karta hai.

Example:

R1 = R2 + R3    ; A: produces R1
R4 = R1 * R5    ; B: reads R1  -> B truly depends on A

Picture yeh hai: A se B ki taraf ek arrow jo kehta hai "value yahan flow hoti hai." Yeh arrow delete nahi ho sakta — yeh real data flow hai.

WAW (Write-After-Write): dono ek hi box mein likhte hain.
WAR (Write-After-Read): ek box mein likhta hai jo order mein baad wala already read kar chuka hai.

R1 = R2 + R3    ; A: writes R1
R1 = R6 - R7    ; C: also writes R1  -> WAW, lekin A aur C koi real data share nahi karte

Picture yeh hai: A aur C dono ek hi box R1 mein point karte hain, lekin A aur C ke beech koi arrow nahi hai. Clash sirf box ke naam ki wajah se hai, kisi number ki wajah se nahi.

Topic ko yeh distinction kyun chahiye: true dependencies unbreakable skeleton hain; false ones hataane wala clutter hain. OoOE (5.3.04-Register-renaming) ka poora trick yahi hai ki false ones ko mita do taaki sirf true skeleton speed ko limit kare.

4. Architectural vs physical registers — naam/box ka split

Relationship, symbols mein: $(physical register count) ≫ (architectural register count)$ Yahan $≫$ padha jaata hai "much greater than"— sirf bada nahi, balki bahut bade factor se bada.

Picture yeh hai: 32 labelled name-tags (architectural) lekin ek bada pool of 168 unlabelled boxes (physical). Ek chota sa map decide karta hai kaunsa tag abhi kaunse box ko point kar raha hai.

Topic ko yeh kyun chahiye: kyunki real boxes names se zyada hain, CPU har write ko uska apna private box de sakta hai. Isliye renaming possible bhi hai. Poora mechanics 5.3.04-Register-renaming mein hai.

5. Common Data Bus (CDB) aur "snooping"

Jab instructions out of order run ho jaayein, toh ek finished result har us instruction tak pahunchna chahiye jo uska intezaar kar rahi hai, jaldi se.

Picture yeh hai: ek loudspeaker (bus) announce kar raha hai "instruction P3 ka jawab 42 hai!", aur sunne walon se bhara ek room; sirf woh react karte hain jinhe P3 ki zaroorat thi.

Wake-up rule ko plain symbols mein likh sakte hain. Maano $I$ ek waiting instruction hai jiska ek operand producer $P_{j}$ se aane wala tagged hai. Jab $P_{j}$ value $V$ broadcast kare: $if operand of I is tagged P_{j} \Rightarrow operand \leftarrow V, ready \leftarrow true$

Symbols padhein:

$\Rightarrow$ matlab "implies / then"
$\leftarrow$ matlab "gets set to"
$ready$ ek true/false flag hai: kya is operand ko abhi uski value mili hai?

Saab ko ek saath broadcast kyun, ek ek ko kyun nahi? Kyunki kaafi saari instructions ek hi result ka intezaar kar sakti hain. Unhe parallel mein jagana ek slow chain of one-at-a-time nudges se bachata hai.

6. Logic symbols — ready condition padhna

Parent yeh likhta hai: $Ready (I) = Ready (src_{1}) \land Ready (src_{2})$

Har piece decode karo:

$Ready (I)$ — ek true/false sawaal: "==kya instruction $I$ run karne ki allowed hai?=="
$src_{1}, src_{2}$ — do input operands (do values jo woh add/multiply karti hai).
$\land$ — logical AND: tabhi true jab dono sides true hon.

Toh plain words mein: ek instruction ready hai exactly jab uske dono inputs ready hon. Simple hai, lekin $\land$ aur true/false idea aapka hona chahiye ise padhne ke liye.

7. In-order commit aur precise exceptions

Out of order run karne ka matlab finish bhi out of order hona hai. Lekin bahari duniya ko kabhi yeh gandagi nahi dikni chahiye.

Picture yeh hai: ek queue jahan instructions back rooms mein kisi bhi order mein compute kar sakti hain, lekin woh sirf front door (commit) se ek ek karke, original order mein, bahar nikal sakti hain. Agar door wali instruction fault karti hai, toh us ke peeche wali sab throw away ho jaati hain, jaise unhone kabhi "hua" hi nahi.

Topic ko yeh kyun chahiye: yahi woh promise hai jo OoOE ko invisible rakhne deta hai. Yeh 5.3.03-Speculative-execution ko bhi underpin karta hai, jahan CPU aise guesses run karta hai jo discard kiye ja sakein.

8. IPC — woh scoreboard jise hum raise karna chahte hain

Picture yeh hai: instructions completed (numerator) divided by elapsed ticks (denominator). Idle ticks ko useful kaam se bharna IPC badhata hai. Har cycle mein zyada instructions squeeze karna exactly 7.1.01-Instruction-level-parallelism hai, aur ek saath kaafi karne ke liye 5.3.01-Superscalar-architecture chahiye.

Foundations topic ko kaise feed karti hain

Upar se neeche padho: raw atoms (instructions, order, latency) dependency ka idea create karte hain; dependencies renaming ko motivate karti hain (physical boxes + RAT); renaming aur ready rule aur broadcast bus out-of-order running possible banate hain; in-order commit ise safe rakhta hai; aur payoff hai zyada IPC.

Equipment checklist

Khud test karo — right side cover karo aur reveal karne se pehle zor se jawab do.

Ek phrase mein instruction kya hota hai?

Ek choti si CPU command (jaise add, load) — programs inki lists hain.

"Program order" ka matlab kya hai?

Woh exact upar-se-neeche order jisme programmer ne instructions likhe.

Clock cycle vs latency kya hai?

Cycle clock ki ek tick hai; latency woh ticks hain jo ek instruction ko chahiye.

Kaunsi dependency real hai aur hataayi nahi ja sakti?

True (RAW) dependency — B woh padhta hai jo A ne likha.

Kaunsi dependencies fake hain aur inhe kaise hataya jaata hai?

WAR aur WAW — register name reuse karne se hoti hain; ek fresh physical register (renaming) de kar hatayi jaati hain.

Physical registers architectural se zyada kyun hote hain?

Taaki har write ko apna private box mile, false name-clash dependencies khatam hon.

RAT kya karta hai?

Har architectural register name ko us physical box par map karta hai jo woh abhi mean karta hai.

Ready (I) = Ready (src_{1}) \land Ready (src_{2})

ko words mein padho.

Ek instruction ready hai tabhi jab uske DONO input operands ready hon.

"Much greater than" ka symbol kya hai aur kahan use hota hai?

≫

— physical registers

≫

architectural registers.

Common Data Bus kya karta hai, aur snooping kya hai?

CDB ek finished result ko ek saath saari waiting stations par broadcast karta hai; snooping woh hai jab har station us tag ke liye sunta hai jiska use zaroorat hai.

Commit program order mein kyun hona chahiye?

Precise exceptions rakhne ke liye aur reordering ko bahari duniya se invisible rakhne ke liye.

IPC kya hai aur hum care kyun karte hain?

Instructions finished per clock cycle — woh throughput scoreboard jise OoOE raise karna chahta hai.

Aage: in atoms ko samajhne ke baad, Out-of-order execution par wapas jao aur Tomasulo section padho — wahan ka har symbol ab ek meaning aur ek picture rakhta hai.